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Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit - - PowerPoint PPT Presentation

Nov 19, 2023 111 likes •773 views

Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications Paul Muller Microelectronic Systems Lab (LSM) cole Polytechnique Fdrale de Lausanne (EPFL) Contributors Matthew K. Emsley and Prof. M.

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SLIDE 1

Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications

Paul Muller

Microelectronic Systems Lab (LSM) École Polytechnique Fédérale de Lausanne (EPFL)

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SLIDE 2

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 2

Contributors

  • Matthew K. Emsley and Prof. M. Selim Ünlü

Boston University Photonics Center Boston, MA, USA

  • Armin Tajalli, visiting Ph.D. student

Sharif University of Technology Teheran, Iran

  • Prof. Yusuf Leblebici, Ph.D. thesis advisor

École Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland

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SLIDE 3

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 3

Motivation (1/2)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 4

Motivation (2/2)

  • Transistor count grows exponentially (Moore)
  • I/O count grows with perimeter (Rent)
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SLIDE 5

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 5

Current Server Interconnects

  • Electrical and Optical

L.Buckman et al., Parallel Optical Interconnects, CLEO 2000 Silicon Graphics Inc., Web Site

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 6

Next-Generation Chip-to-Chip Links

H.Takahara, Optoelectronic Packaging Trends in Japan , Stanford University, US-Asia TMC, May 2003

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SLIDE 7

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 7

Outline

  • Motivation
  • Particularities of Short-Distance Links
  • Pure Silicon Photodetectors
  • Transimpedance and Limiting Amplifier

Design

  • Gated Oscillator CDR
  • Conclusion
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SLIDE 8

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 8

Outline

  • Motivation
  • Particularities of Short-Distance Links
  • Pure Silicon Photodetectors
  • Transimpedance and Limiting Amplifier

Design

  • Gated Oscillator CDR
  • Conclusion
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SLIDE 9

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 9

Optical Receiver Overview

TIA CDR DATA CLK LA Traditionally BiCMOS InGaAs

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SLIDE 10

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 10

Optical Receiver Overview

TIA CDR DATA CLK LA Si CMOS All in CMOS

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 11

Multi-Channel Requirements

  • Low cost

– Standard CMOS (at least compatible) – Low area (no inductors?)

  • Low power (inductors?)
  • Designed for use as IP

– Simple use – Compliant with standard P&R and floorplanning (minimum inter-channel routing constraints) – Robustness

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SLIDE 12

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 12

Crosstalk

  • Substrate crosstalk an issue in CMOS (no

deep trenches) – SOI would solve this issue

  • Differential topologies minimize supply

crosstalk

  • Magnetic coupling through inductors?
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SLIDE 13

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 13

Synchronicity / Plesiochronicity

D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 Db+ Db- Da+ Da-

16-bit synchronous parallel bus 2-channel serial link

slower (fB - ∆f) faster (fB + ∆f)

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SLIDE 14

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 14

Eye Diagram

A unit interval (UI) is equal to an average bit period

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SLIDE 15

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 15

Jitter and Probability Density Functions

  • Random jitter (RJ)

– Has a Gaussian distribution – Amplitude measured in UIRMS

  • Deterministic jitter (DJ)

– Considered uniform – Amplitude measured in UIPP

  • Sinusoidal jitter (SJ)

– Sine-wave phase modulation – Amplitude measured in UIPP

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SLIDE 16

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 16

Jitter Tolerance (JTOL)

[InfiniBandTM Specification] – Data Rate 2.5Gb/s

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 17

Data Encoding

  • 8b/10b data encoding
  • Loss of bandwidth (20%), e.g. InfiniBand™:

– Signal rate 2.5 GBd – Effective data rate 2.0 Gb/s

  • Transition density = 0.6
  • DC balance
  • Limited low-frequency spectral content
  • Maximum run length of 5 bits (K28.5 pattern)

…00111110101100000101…

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SLIDE 18

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 18

Outline

  • Motivation
  • Particularities of Short-Distance Links
  • Pure Silicon Photodetectors
  • Transimpedance and Limiting Amplifier

Design

  • Gated Oscillator CDR
  • Conclusion
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SLIDE 19

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 19

Resonant Cavity Enhancement

Bandwidth-efficiency tradeoff in standard silicon PIN photodetectors ⇒ insufficient efficiency at high data rates ⇒ implementation of a resonant cavity to increase the light path distance in the absorption region

Incident light

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SLIDE 20

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 20

Resonant Cavity Enhancement

A Fabry-Perrot cavity using two Bragg reflectors is built into the silicon photodetector

Silicon Substrate

p+ region n+ region

n+ contact implant p+ contact n+ contact SiO2 Si SiO2 Si Photodetector Window

     mirror lower

interface) Air Si ( −

mirror upper

Incident light

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SLIDE 21

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 21

Silicon-Only Photodetector

The integrated resonant cavity improves the detector efficiency dramatically

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SLIDE 22

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 22

12x1 Photodiode Array

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SLIDE 23

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 23

Outline

  • Motivation
  • Particularities of Short-Distance Links
  • Pure Silicon Photodetectors
  • Transimpedance and Limiting Amplifier

Design

  • Gated Oscillator CDR
  • Conclusion
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SLIDE 24

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 24

Gain-Bandwidth Tradeoff

  • Limiting amplifier performance determined by the achievable

gain-bandwidth product target: BWtot = 4.5GHz Av0 = 29dB

  • Optimum gain per stage for cascaded topologies ≅ 2 [T. H. Lee]

but BWtot < 2GHz

  • Available trade-off improvements

– Increased supply voltage ⇒ reliability issues – Cherry-Hooper topology ⇒ suffers of shrinking supplies – Active inductors ⇒ require high gate voltage – Spiral inductors ⇒ silicon area (?), design parameters (?) – Inter-stage downscaling

⇒ Comparative Study of Inductorless and Inductive Peaking Topologies

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 25

Inductorless Limiting Amplifier

For 1st-order stages with identical gain and cut-

  • ff frequency:

1 2

1

− ⋅ = = = ∏

= N ci N i N DCi DCi DC

f BW Av Av Av

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SLIDE 26

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 26

Amplifier Optimization (1/3)

( )

N N W mu DC

h C h BW g Av       − ⋅ ⋅ + ⋅ ⋅ ⋅ ⋅ = 1 2 1 1 2 α π

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SLIDE 27

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 27 load in N load in

W W h C C = =

Amplifier Optimization (2/3)

Considered Solution

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SLIDE 28

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 28

∑

= −

=

N n n tot

h P P

1 1

Amplifier Optimization (3/3)

Considered Solution

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SLIDE 29

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 29

Inductive Peaking Amplifier

  • Same cascaded amplifier topology, but no inter-stage scaling
  • Inductors need a lot of silicon area
  • Lower bias currents ⇒ reduced device area
  • Absence of reliable model parameters ⇒ conservative design
  • High Q-factor is not needed ⇒ further area reduction possible
  • Risk of magnetic coupling?

1 3 2

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SLIDE 30

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 30

Simulated Transfer Function

with L without L AvLA [dB]

100M 10G f [Hz] 1M

10 30 20

  • 30
  • 10
  • 20
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SLIDE 31

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 31

Amplifier Layouts

840µm 470µm Inductorless Amplifier Inductive Peaking Amplifier 1160µm 440µm

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SLIDE 32

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 32

Inductorless LA Results

1UI = 400ps

22mV 400ps

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 33

Inductive Peaking LA Results

221mV 400ps

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SLIDE 34

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 34

Coupling Measurements

20mV 100mV Channel 1 Input Channel 2 Output

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SLIDE 35

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 35

Summary of Results

  • 0.51

0.18µm Digital CMOS Technology 11.0 30.5? 2.3 0.6 Input Ref. Noise @1GHz [nV/√Hz] with L w/o L with L w/o L Amplifier Type 1.98 max 7.5 23 4.5 1.62 min 1.98 max 60 25 3.7 1.62 min Simulation 20 4? Voltage Gain [dB] Measurement 0.40 20 1.5 1.6 min 2 max 2.0 max 6.4 1 1.6 min Area [mm2] Supply Voltage [V] IVDD [mA] @ 25°C Bandwidth [GHz]

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SLIDE 36

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 36

Transimpedance Amplifier

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 37

ZTIA [dBΩ]

Simulated Transimpedance Gain

1E8 1E10 40 80 f [Hz] 1E6

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SLIDE 38

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 38

Measured “Eye” Diagram

CIN≈0.2pF fb=2.5Gb/s

25mV 400ps Simulated with CIN=0.8pF

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SLIDE 39

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 39

Die Microphotograph

TIAs LAs

50Ω Drivers Bias 470µm 530µm

C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 1

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SLIDE 40

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 40

Outline

  • Motivation
  • Particularities of Short-Distance Links
  • Pure Silicon Photodetectors
  • Transimpedance and Limiting Amplifier

Design

  • Gated Oscillator CDR
  • Conclusion
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SLIDE 41

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 41

Digital Core with Serial I/O

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 42

Gated Oscillator (1/2)

  • A large number of small

and low-power CDR blocks

  • Control current from

shared PLL used to match clock frequencies

  • f all channels
  • Only low-frequency

control signals are routed between the blocks

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SLIDE 43

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 43

Gated Oscillator (2/2)

  • 1

DDin EDET Din CKout

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 44

Design Methodology

CDR Topology Statistical Simulation Transistor-Level Simulation Behavioral / Temporal Simulation Layout Post-Layout Simulation CDR Topology Statistical Simulation Transistor-Level Simulation Behavioral / Temporal Simulation Layout Post-Layout Simulation

  • Important design parameters for short-

distance CDR designs

– Jitter tolerance – Frequency tolerance – Power / Si area

  • CDR power budget per link

Pdiss < 5 mW / Gbps / Channel

  • The Gated Oscillator CDR is a good

candidate

  • But can it comply with the jitter and

frequency tolerance specifications?

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 45

Jitter Statistics

0.01 UIRMS Oscillator (CKJ) swept UIPP Sinusoidal (SJ) 0.021 0.3 UIRMS UIPP Random (RJ) 0.4 UIPP Deterministic (DJ) Value Units Jitter Type

RJ only RJ+DJ (here 0.2UIpp)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 46

Sinusoidal Jitter (1/2)

  • Knowledge of the sampling interval makes SJ a deterministic

process

  • Conventional SJ PDF cannot be considered (would be

excessively stringent)

  • Exact SJ PDF is computed as a function of SJamp, SJfreq and CID
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SLIDE 47

CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 47

Sinusoidal Jitter (2/2)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 48

Gated Oscillator Statistical Model (1/3)

  • Jitter tolerance estimation with low simulation time
  • Bathtub curve for n consecutive identical digits (CID)
  • BER is the sum weighted by their probability of
  • ccurrence
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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 49

Gated Oscillator Statistical Model (2/3)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 50

Gated Oscillator Statistical Model (3/3)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 51

BER with 1% Frequency Offset

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 52

Time-Domain Model

  • VHDL-based
  • Jitter modeled as time-

variant bit period

  • Important cell delays

taken into account

  • Same jitter

specifications as for Matlab model

architecture bhv of cdr_gcco is begin -- ring_osc calc_delay0: process begin -- process calc_delay awgn(seed1, seed2, mean, sigma, jitter); delay0 <= 1 ps * 1.0e12/ (8.0*(cdr_gcco_fc+cdr_gcco_k* (cctrl-cdr_gcco_cc0))) * (1.0+jitter); wait for delay0; end process calc_delay0; […] -- calculation of the 3 cell delays vinv1 <= transport (vinv4 and cdr_gcco_trig) and (cdr_gvco_enable and cdr_gcco_nreset) after delay0; vinv2 <= transport not(vinv1) after delay1; vinv3 <= transport not(vinv2) after delay2; vinv4 <= transport not(vinv3) after delay3; cdr_gcco_ckout <= not(vinv4); end bhv;

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 53

Edge Detector Delay

  • Should be delay insensitive
  • EDET -> CKout race

EDET VCO2 CKOUT VCO1 VCO3

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 54

Optimum Sampling Point (1/3)

Improved Symmetry around UI/2

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 55

Optimum Sampling Point (2/3)

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 56

Optimum Sampling Point (3/3)

But: BERinit = 1.13 ·10-11 → BERnew = 2.70 ·10-4 !!!

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 57

Oscillator Jitter

  • Accumulated jitter during free running:

T

ck

∆ = κ σ

  • Free running interval given by data encoding
  • κ defined by design (based on Hajimiri):

          + ∆ =

SS L SS

I R V I kT 1 1 3 8

min

γ η κ

8

10 4 . 9

−

× ≤ κ

  • For FTOL ≈ 9%:
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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 58

Phase Noise Estimation

maximum acceptable κ

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 59

Oscillator Cell with Replica Bias

+ VA

  • VB

+ Vsel VDD Vout+ ISS Vout- Av +

  • Replica Bias

Delay Cell VREF ICTL VSS

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 60

Shared PLL Layout

Loop Filter CCO 300µm 320µm Divider

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 61

Gated Oscillator Layout

440µm 240µm Oscillator Clock 50-Ohm Buffer Data 50-Ohm Buffer

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 62

Chip Layout

Shared PLL Clock Recovery Channels 0-6 Test Oscillator BIAS

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 63

Summary of CDR Simulation Results

1.3 Settling Time [µs] 0.10 Area [mm2]

Shared PLL

156.25 Reference Clock [MHz] 0.06 Area [mm2] (Core) 2 1.6 Supply Voltage [V] 6.4

max

8.1 2.5

min

0.18µm Digital CMOS Technology

1 CDR channel

IVDD [mA] @ 25°C IVDD [mA] @ 25°C Data Rate [Gb/s]

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 64

Preliminary CDR Measurement Results

Recovered Data (Shifted) Input Data

200 mV

  • 200 mV

50ns (5ns/div) ≡ 2.5Gb/s

400 mV

  • 400 mV

0 mV

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CMOS Multi-Channel Single-Chip Receiver for Optical Data Comms 65

  • We introduced some of the design issues in

multi-channel photonic receivers

  • Gain and bandwidth specifications of TIA and

LA in standard CMOS remain challenging

  • The jitter and frequency tolerance analysis

flow gives a-priori information

  • n

the advantages and limitations of the selected gated oscillator CDR topology.

  • This work shows challenges and solutions for

the design of fully integrated CMOS multi- channel fiber-optic receivers

Conclusion