Stage Fractional- N Injection-Locked PLL Using Soft Injection - - PowerPoint PPT Presentation

Matsuzawa & Okada Lab.

b.

y

Matsuzawa & Okada Lab.

b.

y

An Automatic Place-and-Routed Two- Stage Fractional-N Injection-Locked PLL Using Soft Injection

Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan

1S-1

2

Synthesizable Analog Circuits

1S-1

GDS Digital design flow

e.g. Encounter, IC Complier, Design Compiler, PrimeTime, Commercial P&R tools…

HDL

module PLL

(CLK, …, OUT) …

endmodule

with a standard-cell library without any custom-designed cells without manual placement

[W. Deng, et al., ISSCC 2014]

3

Integer-N IL-PLL Operation

1S-1

Reference VCO Reference D D D D ...

e.g. N=3+(1/M)

2·Tref 3·Tref N·2ɽ 2N·2ɽ 4N·2ɽ fPLL=N·fref Tref 4·Tref 5·Tref

fPLL t

3N·2ɽ P0 P0 P0 P0 P0

P0  P0  P0  P0  P0  P0 …

Phase Domain (Integer-N)

4

Sub-Integer-N IL-PLL Operation

1S-1

Reference D D D D ... ... P0 P1 P2

e.g. N=3+(1/M)

Reference VCO P0 P1 P2

...

[P. Park, et al., ISSCC 2012] fPLL=(N+1/M)·fref (N+1/M)·2ɽ 2·Tref 3·Tref Tref 4·Tref 5·Tref

fPLL t

2·(N+1/M)·2ɽ 3·(N+1/M)·2ɽ 4·(N+1/M)·2ɽ P1 P2 P3 P4 P0

Phase Domain (Sub-Integer-N) P0  P1  P2  P3  …  P0  P1 …

5

Phase Domain (Fractional-N)

P0  P0  P1  P1  P2  P2  P3 …

fPLL=(N+0.5/M)·fref N·2ɽ 2·Tref 3·Tref Tref 4·Tref 5·Tref

fPLL t

(2·N+1/M)·2ɽ (3·N+1/M)·2ɽ (4·N+2/M)·2ɽ P0 P1 P1 P2 P0

1S-1

6

Proposed Soft Injection

Soft Injection Reference Injection Signal

Reference Locked Soft Injection signal

1S-1

7

Proposed Soft Injection

1S-1

[W. Deng, et al., ISSCC 2015]

Injection at f8 (Dsub=7, DDSM=1) Injection at f0 (Dsub=0, DDSM=0) Soft injection f8 w/o injection Reference f8 w/ injection1 “hard” injection TVCO f8 w/ injection TVCO

28 27

f8 w/ injection2 “soft” injection

8

Design Procedure and Chip Microphoto

1S-1

Verilog netlist (gate-level) Verilog netlist (gate-level)

DCO DAC Logic Logic Logic Synt. Tool GDSII P&R Tool Netlist

Verilog RTL

275mm 175mm

CMOS 65nm technology Design Procedure

9

Performance Comparison

1S-1

*FOM is calculated based on RMS jitter. This work Deng ISSCC2014 Marucci ISSCC2014 Elkholy ISSCC2014 CMOS Tech. 65nm 65nm 65nm 65nm Power [mW] 3 @1.5222GHz 0.78 @0.9GHz 3 @1.7GHz 10.5 @0.58GHz Spur [dBc]

• 53
• 47
• 51

N/A FoM [dB]

• 224.2
• 236.5
• 232
• 221.9

Type Frac-N Int-N Frac-N Frac-N Topology Soft Injection Injection locking DTC-based MDLL Injection locking

FoM=10log[(jt/1s)2(PDC/1mW)]

10

Conclusion

• A synthesizable fractional-N IL-PLL

with a soft-injection locking technique is presented.

• The proposed fractional-N IL-PLL can

achieve fine resolution, low spur with comparable FoM.

1S-1