A Dual-loop Injection-locked PLL with All-digital Background - - PowerPoint PPT Presentation

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A Dual-loop Injection-locked PLL with All-digital Background - - PowerPoint PPT Presentation

May 31, 2023 509 likes •592 views

A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan

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SLIDE 1

Matsuzawa & Okada Lab.

ab.

  • logy

Matsuzawa & Okada Lab.

ab.

  • logy

A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan

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SLIDE 2

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Injection-Locking Technique

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SLIDE 3

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Issue of Injection-locked PLL

Conventional PLL Conventional IL-PLL

Cannot track frequency drift Can track frequency drift

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SLIDE 4

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Proposed Dual-loop Architecture

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SLIDE 5

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PVT Tracking Capability

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SLIDE 6

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Performance Comparison

Ref. [1] [2] [3] This Work Power [mW]

0.89 1.35 12 6.9 0.97

Area [mm2]

0.25 0.25 0.058 0.03 0.0022

  • Integ. Jitter [pS]

0.4 3.2 0.68 2.4 0.7

FOM [dB]

  • 249
  • 229
  • 234
  • 225
  • 243
  • The proposed dual-loop IL-PLL with PVT

calibration system can be well suited for low-jitter and small-area clock generation.

[1] A. Elshazly, et al., ISSCC 2012 [2] B. Helal, et al., JSSC 2008 [3] C. Liang, et al., ISSCC 2011