Spiral 2-7 Capacitance, Delay and Sizing 2-7.2 Learning Outcomes - PowerPoint PPT Presentation

2-7.1 Spiral 2-7 Capacitance, Delay and Sizing

2-7.2 Learning Outcomes • I understand the sources of capacitance in CMOS circuits • I understand how delay scales with resistance, capacitance and voltage • I can determine appropriate width of PMOS and NMOS transistors based on the configuration of the transistors and given current conduction parameters • I understand how fan-in and fan-out affect the delay of a circuit – I understand how to use sizing to drive larger fan-out loads • I understand the sources of static and dynamic power consumption and how they are affect by changes in various parameters

2-7.3 WHAT IS CAPACITANCE?

2-7.4 Capacitance Res. Conductive • Capacitors are formed by separating Material two conductive substances with an + + + + E y insulator - - - • Capacitors “store” charge Insulator - • Capacitance measures how much Material charge is needed to achieve a Connected to a source, charge will be stored certain voltage (electric potential) on the conductive plates creating a positive – C = Charge (Q) / Voltage (V) voltage between the conductive plates • Capacitance measured in Farads (F) Res. + + + - - - C To change the voltage at the capacitor we Capacitor Schematic must change the voltage (if we turn off the Symbol voltage source charge will drain off the capacitor)

2-7.5 Charging/Discharging Capacitors • Charging a capacitor gets more “difficult” as more charge is added • Eventually, no more charge can be added and the capacitor acts like an open circuit + + + + + + - - - Voltage of Capacitor + + + + + + - - - - - - As more charge (voltage) builds up that charge repels like charge and makes it “harder” to add more (like pushing a spring) Time

2-7.6 Capacitor I-V Relationship 𝑅 • Fact 𝐷 = 𝑊 , or 𝑅 = 𝐷𝑊 𝑅 𝑢 = 𝑒𝑅 • Also recall 𝑗 = 𝑒𝑢 • Thus, substituting 𝑗 = 𝑒𝑅 𝑒𝑢 = 𝐷 𝑒𝑊 𝑒𝑢 • Current is linearly related (slope = C) to the change in voltage (not the absolute voltage) – No voltage change (constant voltage) means no current will flow

2-7.7 Measures of Capacitance 𝐵𝜁 + + • C = + - - - 𝑒 – 𝜁 is the permittivity of the insulator substance (intrinsic material property) • 𝜁 defined as 1 for a vacuum • Silicon dioxide (separates gate from silicon) = 3.9 • Pure silicon = 11.68 – 𝐵 is the area of the conductive materials – 𝑒 is the separation distance (or thickness of the capacitor)

2-7.8 First-order RC circuit step response RC CIRCUIT ANALYSIS

2-7.9 Resistance / Capacitance Analogy + + + Resistance = Limit of water flow Charge = Water Voltage Source = Water Pressure Capacitance = Total Water Needed Switching Time = Time to fill or drain the capacitor (“bucket”) of charge Thus, increase the voltage or decrease the resistance/capacitance.

2-7.10 Voltage, Resistance & Capacitance • Let's analyze a simple circuit – Known as an RC circuit (resistor & capacitor in series) – Assume t < 0, Vs = 0 then Vc=0 – For t > 0, Vs = Vdd (voltage source turns on) – Current through R must be same as current "through" C 𝑊 𝑆 𝑒𝑊 𝑊 𝑒𝑒 −𝑊 𝑒𝑊 • 𝑗 = 𝑑 𝑑 𝑑 𝑆 = 𝐷 ⇒ 𝑗 = = 𝐷 𝑒𝑢 𝑆 𝑒𝑢 – Now let's solve for dVc/dt 𝑒𝑊 𝑊 𝑒𝑒 −𝑊 • 𝑑 𝑑 𝑒𝑢 = 𝑆𝐷 – We can solve this differential equation 𝑒𝑒 𝑓 − 𝑢 • 𝑊 𝑑 𝑢 = 𝑊 𝑒𝑒 + 𝑊 𝑑 0 − 𝑊 𝑆𝐷 𝑒𝑒 1 − 𝑓 − 𝑢 • For Vc(0)=0 we have 𝑊 𝑑 𝑢 = 𝑊 𝑆𝐷

2-7.11 Voltage, Resistance & Capacitance • Let's analyze a simple circuit – Known as an RC circuit (resistor & capacitor in series) – Assume t < 0, Vs = Vdd then Vc=Vdd – For t > 0, Vs = 0 (voltage source = GND) – Current through R must be same as current "through" C 𝑊 𝐷 𝑒𝑊 𝑊 𝑒𝑒 −𝑊 𝑒𝑊 • 𝑑 𝑑 𝑑 𝑆 = −𝐷 ⇒ 𝑗 = = 𝐷 𝑒𝑢 𝑆 𝑒𝑢 – Now let's solve for dVc/dt 𝑒𝑊 𝑊 𝑒𝑊 𝑊 • 𝑑 𝑑 𝑑 𝑑 𝑒𝑢 = − ⇒ 𝑒𝑢 + 𝑆𝐷 = 0 𝑆𝐷 – We can solve this differential equation 𝑑 0 𝑓 − 𝑢 • 𝑊 𝑑 𝑢 = 𝑊 𝑆𝐷 𝑒𝑒 ∙ 𝑓 − 𝑢 • For Vc(0)=Vdd we have 𝑊 𝑑 𝑢 = 𝑊 𝑆𝐷

2-7.12 Time Constant • Notice the charging (discharging) time is determined by product of R*C • We refer to this as the time constant, τ – τ = RC • As the product of RC increases we get slower switching times • We can show that the time it takes to charge/discharge a capacitor to a fraction of Vdd is given in the table below Voltage Range Time 0 to 50% (t p = prop. delay) 0.69*RC 0 to 63% ( τ ) RC 10% to 90% (t r =rise time/delay) 2.2*RC

2-7.13 DELAY

2-7.14 MOSFET Parasitic Capacitance • In order to examine the delay of a MOSFET, we have to determine nature and amount of parasitic capacitance associated with MOS transistor – Parasitic: Unintentional, naturally occurring capacitors – It's not that we want caps, we're stuck with them due to the structure of the MOSFET. • The oxide layer separating gate and substrate is a more obvious capacitor • However the depletion regions around the source and drain also form capacitors Gate Source Drain 14

2-7.15 Transistor R and C values • Observation: Output of one transistor usually drives input of another – Sources of resistance • Channel between source and drain • Wire connecting drain to gate of next transistor – Sources of capacitance • Gate input of the next transistor • Other small capacitances Charge must be conducted through this path and build up at the gate input to raise the voltage to the necessary value 3V Source Metal Wire Gate Gate Source Drain Source Drain

2-7.16 Resistor and Capacitor Delay • Outputs connect to other inputs • Wire from an output To change the output voltage (really of another gate the input of the next gate), we must conduct enough charge to raise or + + lower its present voltage Wire + • Resistance limits the amount of charge that can be transferred per Desired Transition: 0V -> Vdd unit time • Capacitance determines how much charge must be present to attain a certain voltage • Time it takes to attain a certain voltage is proportional to R*C Switching Time ~ Resistance*Capacitance

2-7.17 Where RC Circuits Occur • Consider a CMOS gate driving others (loads) – The output connects to the gate inputs of the loads (fan- out) and thus can be modeled as a capacitive load (C L )

2-7.18 Where RC Circuits Occur • Depending on the inverter input the PMOS or NMOS will be in resistive mode and can be modeled as resistors – Thus we have an RC circuit either charging or discharging the output (C L )

2-7.19 Defining Delays • We model – The next gate(s) and other parasitic capacitances as a lumped capacitance – The PDN or PUN transistors as resistors (since they are operating in linear mode when the input is near VDD or GND) • t PLH and t PHL refer to the propagation delay of a circuit when the output changes from low to high (0→1) [ t PLH ] or high to low (1→0) [ t PHL ] 𝐷 𝑀 𝑊 𝐸𝐸 – 𝑢 𝑄𝑀𝐼 ≈ 0.69𝑆 𝑄 𝐷 𝑀 = 2 𝑙 𝑞 𝑊 𝐸𝐸 −𝑊 𝑈𝑞 Vin t phl 𝐷 𝑀 𝑊 𝐸𝐸 – 𝑢 𝑄𝐼𝑀 ≈ 0.69𝑆 𝑂 𝐷 𝑀 = 𝑙 𝑜 𝑊 𝐸𝐸 −𝑊 𝑈𝑜 2 Vout • We say the delay of the gate is then: – t PD ≈ ( t PLH + t PHL ) / 2 Vin • Important: What reduces delay? t plh Vout – C L  , W/L  , Vdd 

2-7.20 CMOS SIZING

2-7.21 Sizing – PMOS is Slower than NMOS! • Recall the equations for current through a transistor in linear mode 1 𝑋 – |𝐽 𝑒𝑡 | = 𝑒𝑡 | 2 2 𝐿′ 2 𝑤 𝑕𝑡 − | 𝑊 𝑈 | |𝑊 𝑒𝑡 | − |𝑊 𝑀 1 𝑋 – Ohm's law says I = V/R so in the equation above 𝑆 ∝ 𝐿′ 𝑀 • Problem K N > K P (K N ≈ 2.5K P ) – PMOS are worse at conducting than NMOS VDD – This will leave to imbalances in delay (i.e. t PLH > t PHL ) – To balance the delay when pulling up vs. pulling down OUT we can play with Width IN • Solution: Make W P > W N by about a factor of 2 or 2.5 CL

2-7.22 Sizing – Inverter • Assume K K  n p 2 • Find the ratio and W p and W n that balances the delay of output during falling and rising transitions R 1 2 KW K W W       p n n n W 2 W p n R L R K W W n p p p

2-7.23 Sizing – Simple CMOS Gates • Goal: Make any gate have the same worst case resistance as an inverter • The ratio of the {W/L} PUN / {W/L} PDN should be about two (or higher) to make up for slow PMOS Important Notes: For parallel transistors consider only the case if 1 is on (Remember if NOR R||R then Reff=R/2 which is a better case so we assume only one is on) Series transistors in NAND series add lengths/ resistance All paths in a PxN should have same resistance

2-7.24 Sizing – Complex CMOS Gates B 8 6 A 4 3 C 8 6 D 4 6 OUT = D + A • (B + C) A 2 D 1 B 2 C 2 24

2-7.25 Compound Gate Example Y = D • ( A + B + C) A B C D Y D A B C