SoC Design Lecture 10: On-Chip Interconnection Networks Lecture 10: - PowerPoint PPT Presentation

SoC Design Lecture 10: On-Chip Interconnection Networks Lecture 10: On Chip Interconnection Networks Shaahin Hessabi Department of Computer Engineering g g Sharif University of Technology

Signal Transmission on SoC � We focus on global wires � Local wires can scale with technology, and present design styles may still apply. � Global wires are on top level metals (with higher pitch and width). � Increased pitch reduces cross-coupling (improving noise immunity). � Increased width reduces wire resistance. � Increased spacing around the wire prevents capacitance growth. � Inductive effects grows relative to resistance and capacitance. g p � Future global wires modeled as lossy transmission lines, as opposed to RC models. � Causes signal attenuation and dispersion in frequency of fast signals. � Can be reduced by splitting wires in several sections with buffers in between � Can be reduced by splitting wires in several sections with buffers in between. o Impedance matching required due to line inductance. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 2

Signal Integrity � Signal integrity: error-free information transfer (at the physical level) on global wires will become harder, due to: � Signal swings are reduced, with a corresponding reduction in voltage noise margins. � Crosstalk increases. � More EMI because of smaller voltage swings and smaller dynamic storage capacitances. � M EMI b f ll lt i d ll d i t it � More synchronization failures and/or metastability, because of transmission speed changes, local clock frequency changes, timing noise ( jitter), and so on. � Soft errors will be a potential hazard for large SoCs as well. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 3

On-Chip Interconnection Networks Shared-Medium Networks Switched-media Networks (Direct and Indirect Networks) Hybrid Networks Hybrid Networks SoC: On-Chip Interconnection Networks 4 Hessabi@Sharif University of Technology

SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 5

Shared-Medium Networks � Simplest interconnect structures. � Transmission medium is shared by all communication devices. y � Network is usually passive: does not generate control or data messages. � Serialization: Only one component can send a message at any given time. y p g y g � Order of messages. � Interconnection structures: � Point-to-point � On-chip bus � On-chip network � On-chip network SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 6

Types of Busses � Processor-memory bus (design specific). � Short and high speed. � Short and high speed. � Only need to match the memory system. � Maximize memory-to-processor bandwidth. � C � Connects directly to the processor. di l h � Optimized for cache block transfers. � I/O bus (industry standard). I/O bus (industry standard). � Usually is lengthy and slower. � Needs to match a wide range of I/O devices � Needs to match a wide range of I/O devices. � Connects to the processor-memory bus or backplane bus. • Backplane bus (standard or proprietary). � Backplane: an interconnection structure within the chassis. � Allow processors, memory, and I/O devices to coexist. � Cost advantage: one bus for all components � Cost advantage: one bus for all components. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 7

Traditional Bus vs. OCB Traditional Bus (Of aditional Bus (Off-Chip Bus) -Chip Bus) OCB (On-Chip Bus) OCB (On-Chip Bus) � Shared I/O � Routing resource in target device (e.g., FPGA, ASIC) � Fixed interconnection scheme � Bandwidth and latency are � Fixed timing requirement important � Dedicated address decoding SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 8

Off-Chip Bus � Connection of discrete chips on a PCB. � PCI, ISA, … are off-chip busses. � Design Criteria: � High-speed communication between discrete devices (about 30MHz-100MHz). � Minimizing the number of bus signals, i.e., pins, for reducing the cost of PCB. � Minimizing the number of bus signals, i.e., pins, for reducing the cost of PCB. � Tri-state signaling for add-in cards and extensions to disconnect the non-active cards. � PCI uses multiplexed signals for address and data. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 9

On-Chip Busses � No use of tri-state signals : Tri-state bus is difficult for static timing analysis as the bus loading is only identified through dynamic simulation. � High-performance transaction schemes � Point-to-point protocol � Split transaction � Split transaction � Efficient arbitration schemes are adopted. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 10

Shared I/O (Multiplexer Bus vs. Tri-State Bus) / ( p ) � Three-state I/O is slower than direct interconnection. � Solution in OCB: Mux interconnection. � Xilinx design guidelines: recommended, because of technology-independency and more portability. • Multiplexed functional I/O (e.g., address/data) needs more time to transfer data. � Solution in OCB: multiple busses Multiple Multiplexer Bus Multiple Multiplexer Bus r Bus r Bus Three-Stat Three-State Bus e Bus � Bus Masters can send their requests � Only one bus master can output including address and data (for write) address or data (otherwise at the same time. h i collision). � Arbiter selects a bus master. � Bus Grant is needed to output address or data. p SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 11

Physical Constraints � Fixed interconnection scheme: � Traditional busses usually routed across a standard backplane. � OCB allows variable interconnection scheme, defined by system integrator (tool level) � Fixed timing requirement: � Traditional busses have fixed timing requirements: � Highly capacitive and inductive loads. � Designed for the worst case operating conditions, when unknown bus modules are connected together. � OCB has a variable timing specification that: � Can be enforced by place & route tools (tool level). � Usually do not specify absolute timing � Usually do not specify absolute timing. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 12

Bus Components � Switch or node � Arbitration, routing � Converter or bridge (type converter) � From one protocol to another � Size converter � Buffering capacity SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 13

Bussing Strategies � Register-to-Register Communications: � Point-to-point. � Single shared bus. � Multiple special purpose busses. � Tradeoffs between datapath/control complexity and amount of parallelism T d ff b d h/ l l i d f ll li supported by the hardware. Master vs Slave Master vs. Slave � A bus transaction includes two parts: � Master: Issuing the command (and address) – request. g ( ) q � Slave: Transferring the data – action. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 14

A Computer System with One Bus: Backplane Bus p y p � Backplane bus: The most common on chip shared medium architecture � Backplane bus: The most common on-chip shared-medium architecture. � A single bus is used for: � Processor to memory communication. � Processor to memory communication. � Communication between I/O devices and memory. � Low-overhead interconnection for a small number of active processors (i.e., bus masters) and a large number of passive modules (i.e., bus slaves) that only respond to requests from bus masters. � Disadvantages: slow, bus can become a major bottleneck. Di d l b b j b l k � Example: IBM PC. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 15

A Two-Bus System � I/O busses tap into the processor-memory bus via bus adaptors: � Processor-memory bus: mainly for processor-memory traffic. � I/O buses: provide expansion slots for I/O devices. � Apple Macintosh-II: A l M i h II � NuBus: Processor, memory, and a few selected I/O devices. � SCCI Bus: the rest of the I/O devices. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 16

A Three-Bus System � A small number of backplane busses tap into the processor-memory bus: � Processor-memory bus is only used for processor-memory traffic. � I/O buses are connected to the backplane bus � I/O buses are connected to the backplane bus. � Advantage: loading on the processor bus is greatly reduced. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 17

Bus Advantages � Versatility: Any bus is almost directly compatible with most available IPs. � New devices can be added easily. � Peripherals can be moved between computer systems that use the same bus standard. � Low cost: The silicon cost of a bus is near zero. � Bus latency is zero once arbiter has granted control. � Concepts are simple and well understood. SoC: On-Chip Interconnection Networks Hessabi@Sharif University of Technology 18