Low Power and Reliable Interconnection with Low Power and Reliable - - PowerPoint PPT Presentation
Network-on-Chip Symposium, April 2008 Low Power and Reliable Interconnection with Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme Self-Corrected Green Coding Scheme for Network-on-Chip for Network-on-Chip
Network-on-Chip Symposium, April 2008
Low Power and Reliable Interconnection with Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme Self-Corrected Green Coding Scheme for Network-on-Chip for Network-on-Chip
Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang and Wei Hwang
Department of Electronics Engineering & Institute of Electronics, and Microelectronics and Information Systems Research Center, National Chiao-Tung University, HsinChu 300, Taiwan
National Chiao-Tung University 2
NoCS 2008
Introduction Low power joint bus/error correction coding concept
Self-corrected green coding scheme
Triplication error correction coding stage Green bus coding stage
Simulation Results Conclusions
National Chiao-Tung University 3
NoCS 2008
Network-on-chip : an effective
solution to integrate multi-core system and a process independent interconnection architecture. Physical design of NoC
Link wires switch network interface
National Chiao-Tung University 4
NoCS 2008
Three critical issues for on-chip communication
Delay – coupling capacitances Power – parasitic and coupling capacitances Reliability – degrading due to noises
Novel design techniques are proposed to overcome
the crosstalk effect and further provides a reliability bound for on-chip interconnection.
Joint bus and error correction coding schemes
National Chiao-Tung University 5
NoCS 2008
Introduction Low power joint bus/error correction coding concept
Self-corrected green coding scheme
Triplication error correction coding stage Green bus coding stage
Simulation Results Conclusions
National Chiao-Tung University 6
NoCS 2008
Crosstalk Avoidance Code(CAC)
Error Control Code (ECC) Linear Crosstalk Code(LXC)
k l m mc
Crosstalk avoidance codes (CAC)
Avoid specific code patterns or code transitions to reduce delay and power
dissipation.
Error control codes (ECC)
Detect and correct the error bits
Linear crosstalk code (LXC)
Shielding link wires, duplicated bits
National Chiao-Tung University 7
NoCS 2008
physical transfer unit (phit)
the data which is divided and transmitted through micro-network K bits K/N bits
K-to-N serialization
Area Cost (1/N2) Switch delay Crosstalk , signal-to signal skew Signaling Rate
Area Cost (1/N2) Switch delay
National Chiao-Tung University 8
NoCS 2008
Bus Encoder
Serializer
Channels through Multi switch fabrics
Processor Element
interface ECC encoder
Deserializer
interface ECC decoder
ECC decoder ECC encoder ECC encoder ECC decoder
Bus Decoder Switch Fabric Joint bus and error correction coding with serializer/deserializer
Processor Element
Self-corrected green coding scheme
triplication error correction coding stage, green bus coding stage Shorter delay for ECC, more energy reduction and smaller area
National Chiao-Tung University 9
NoCS 2008
Introduction Low power joint bus/error correction coding concept
Self-corrected green coding scheme
Triplication error correction coding stage Green bus coding stage
Simulation Results Conclusions
National Chiao-Tung University 10
NoCS 2008
triplication set
The hamming distance of each set is equal to 3. A constant delay of a majority gate and much smaller than others Rapid correction ability by self-corrected mechanism in bit-level.
National Chiao-Tung University 11
NoCS 2008
Error correction mechanisms
Reducing supply voltage of channels without compromising the reliability of system.
A Gaussian distributed noise voltage VN with variance is added to the signal waveform.
2 N
σ
2
dd n
V Q ε σ ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠
( )
2
2
1 2
y x
Q x e dy π
∞ −
=
,
2 3 triplication
3 2 P k k ε ε ≈ −
Word-error probability : where k : the size of bit-width : bit-error probability
ε
National Chiao-Tung University 12
NoCS 2008
Green bus coding stage
Reducing coupling effect
Establish triplication capacitance matrix Ct by RLC cyclic model Derive power formula with the coefficient α Find the codeword to minimize the value, α Map the codeword to data-word Circuit Implementation Transition definition L X
C C = λ
3 3 3 3
t L
C C λ λ λ λ λ λ λ λ λ λ + − ⎡ ⎤ ⎢ ⎥ − + − ⎢ ⎥ = ⎢ ⎥ − + − ⎢ ⎥ − + ⎣ ⎦
,
Triplication capacitance matrix
1 , 1
C
2 , 2
C
2 , 1
C
4 , 4
C
3 , 3
C
4 , 3
C
3 , 2
C
Approximate Cyclic model Design Flow
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NoCS 2008
Cx
L L H Type1 Type2
Static transitions
Cx
L L H H
Cx
L L Type3
Cx
L H L H Type4 Type5
Cx
L H L H Type3 (no switching or switching in the same direction) signal aliasing
Dynamic transitions
National Chiao-Tung University 14
NoCS 2008
The power consumption can be derived as follow.
2 L DD
P f C V α = ∗ ∗ ∗
( ) ( )
1 2 3 4 5 1 2 2 3 3 4 4 5 12 23 34 45
3( ) 4 r r r r r r r r r r r r r d d d d α λ λ = + + + + + ⊕ + ⊕ + ⊕ + ⊕ + + + + Type 2,5 Type 1 The meaning of is that only one line is changing between two lines as type 1. For the term of , it is about the two lines change in the opposite direction as type2 and type5 transitions.
( )
i j
r r ⊕
( )
ij
d
α is a modified switching activity with considering coupling
capacitances.
National Chiao-Tung University 15
NoCS 2008
National Chiao-Tung University 16
NoCS 2008
More simple and effective Avoid forbidden overlap condition (FOC) and forbidden pattern condition
(FPC) and reduce forbidden transition condition (FTC)
1 2 3 1 2 3 4
Encoder Decoder
National Chiao-Tung University 17
NoCS 2008
Introduction Low power joint bus/error correction coding concept
Self-corrected green coding scheme
Triplication error correction coding stage Green bus coding stage
Simulation Results Conclusions
National Chiao-Tung University 18
NoCS 2008
Energy Reduction to uncoded bus (%)
Simulation Condition : UMC 90nm CMOS technology The length of wires is set as 0.8mm of metal-4 with minimum width and spacing of 0.2um.
X L
C C λ ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠
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NoCS 2008
Voltage of specific error correction coding (k=8)
Voltage (V) 2 3 triplication
3 2 P k k ε ε ≈ −
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NoCS 2008
Voltage of specific error correction coding (k=32)
2 3 triplication
3 2 P k k ε ε ≈ −
Voltage (V)
National Chiao-Tung University 21
NoCS 2008
The proposed self-corrected green coding scheme has the smallest area overhead of codec. For the smallest delay, it is more suitable for the network-
National Chiao-Tung University 22
NoCS 2008
Summaries of different joint coding schemes
Except for s-c green coding, DAP and DSAP, the critical delay of codec depends on the decoder, others are not appropriate for integrating into switch fabrics because of long critical delay .
National Chiao-Tung University 23
NoCS 2008
Introduction Low power joint bus/error correction coding concept
Self-corrected green coding scheme
Triplication error correction coding stage Green bus coding stage
Simulation Results Conclusions
National Chiao-Tung University 24
NoCS 2008
Self-corrected green coding scheme is presented to
construct reliable and low power interconnection for NoC.
Triplication error correction stage
Rapid correction ability to reduce the physical transfer unit size Self-corrected in bit level
Green bus coding stage
More energy reduction by a joint triplication bus power model
Based on UMC 90um CMOS technology, compared to un-
coded code, self-corrected green coding can achieve 34.4% and 67.3% energy saving at voltage 1.2v and 0.84v, respectively.
Network-on-Chip Symposium, April 2008