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Silicon photonics: a new technology platform to enable a new technology platform to enable low cost and high performance photonics photonics L P L. Pavesi i L. Pavesi 18-11-10 Outline Outline Silicon Photonics Silicon Photonics

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SLIDE 1

Silicon photonics:

a new technology platform to enable a new technology platform to enable low cost and high performance photonics photonics

L P i

  • L. Pavesi
  • L. Pavesi

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SLIDE 2

Outline Outline

  • Silicon Photonics

Silicon Photonics

  • State of the art

Sili Ph t i f l b hi

  • Silicon Photonics for lab-on-a-chip
  • NanoSilicon photonics
  • Conclusion
  • L. Pavesi

18-11-10

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SLIDE 3

Outline Outline

  • Silicon Photonics

Silicon Photonics

  • State of the art

Sili Ph t i f l b hi

  • Silicon Photonics for lab-on-a-chip
  • NanoSilicon photonics
  • Conclusion
  • L. Pavesi

18-11-10

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SLIDE 4
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SLIDE 5

Objective: reduce the cost per single transistor

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Objective: reduce the cost per single transistor

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SLIDE 6
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29 January 1969

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SLIDE 7
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SLIDE 8
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SLIDE 9

vs Silicon Photonics

  • vs. Silicon Photonics

Silicon Photonics LD,PD, microrings, Silicon LD,PD, microrings, …. CMOS

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SLIDE 10

Silicon photonics Silicon photonics

Photonic devices produced within standard silicon factory and with y standard silicon processing

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SLIDE 11

Silicon pro’s and cons Silicon pro s and cons

  • Transparent on 1.3-1.5 μm

p μ

  • CMOS compatibility
  • Low cost
  • High index contrast, small footprint
  • No electro-optic effect
  • No detection in 1.3-1.5 μm region
  • High index contrast coupling
  • Lacks efficient light emission
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SLIDE 12

The Opportunity of Silicon Ph i

  • Enormous ($ billions) CMOS infrastructure, process

Photonics

Enormous ($ billions) CMOS infrastructure, process learning, and capacity

  • Draft continued investment in Moore’s law
  • Potential to integrate multiple optical devices

Potential to integrate multiple optical devices

  • Micromachining could provide smart packaging
  • Potential to converge computing & communications

To benefit from this optical w afers

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  • be

e t

  • t

s opt ca a e s m ust run alongside existing product. CMOS PHOTONI CS

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SLIDE 13

Cost = paradigm change Cost paradigm change

  • 200 mm Si wafer has 125,000 - 0.5 mm sized

dies

  • Cost processed CMOS wafers $2,000,000
  • Cost per die: $16
  • Laser size: 10x100 microns.
  • Cost per laser: $ 0.064
  • This is just like estimating the cost of transistors.

They are free. Only the PIC cost matters.

  • Emphasis is moved from components to the
  • L. Pavesi

18-11-10

system

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SLIDE 14

Silicon photonics Silicon photonics

Basic building blocks

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SLIDE 15
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SLIDE 16
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SLIDE 17
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SLIDE 18
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SLIDE 19
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SLIDE 20

Modulator Modulator

Because of its crystal structure, silicon is not a useful conventional electro-optic material useful conventional electro-optic material Because of its indirect bandgap, silicon has no near bandgap nonlinearities near bandgap nonlinearities Thermo-optical effect is strong but slow The only effect that is left is the free carrier or Drude effect

[ ] [ ]

) ( 10 . 6 10 5 . 8 ) ( 10 5 . 8 10 8 . 8

18 18 8 . 18 22

P N P N n Δ + Δ = Δ Δ + Δ x − = Δ

− − − −

α x x x

  • L. Pavesi

18-11-10

R.A. Soref and B.R. Bennett, IEEE JQE 23, 123 (1987)

[ ]

) ( 10 . 6 10 5 . 8 P N Δ + Δ = Δα x x

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SLIDE 21
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SLIDE 22
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SLIDE 23
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SLIDE 24

Photodetection

  • Silicon does not absorb IR well

Silicon does not absorb IR well

Ge Ge Ge Ge Ge Ge

  • Silicon does not absorb IR well

Silicon does not absorb IR well Use hybrid approach Use hybrid approach U SiG i d G U SiG i d G Use SiGe or strained Ge Use SiGe or strained Ge Use damaged silicon Use damaged silicon

Si Si Si Si

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SLIDE 25
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SLIDE 26

Ge photodector Ge photodector

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IEF-LETI

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SLIDE 27
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SLIDE 28

III-V heterogeneous integration for the laser source

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SLIDE 29

III-V heterointegration for the laser source

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SLIDE 30
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SLIDE 31
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SLIDE 32
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SLIDE 33
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SLIDE 34
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SLIDE 35

Where should we integrate the photonics layer ?

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SLIDE 36

Options 1 Options 1

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SLIDE 37

Options 1 Options 1

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SLIDE 38
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SLIDE 39
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SLIDE 40
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SLIDE 41

This requires This requires

Spotsize conversion structures

Lateral coupling Vertical coupling

φ fiber air h g r e φ d

x z y

  • typically based on inverted tapers

t i 3

  • typically based on gratings

t i 10

  • L. Pavesi

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  • spotsize: ~3 µm
  • spotsize: ~ 10 µm
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SLIDE 42
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SLIDE 43

Outline Outline

  • Silicon Photonics

Silicon Photonics

  • State of the art

Sili Ph t i f l b hi

  • Silicon Photonics for lab-on-a-chip
  • NanoSilicon photonics
  • Conclusion
  • L. Pavesi

18-11-10

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SLIDE 44

Explosion of silicon photonics Explosion of silicon photonics

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SLIDE 45

From Building Block Research From Building Block Research

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SLIDE 46

To Large scale integration

Optical Fiber Multiplexor 25 modulators at 40Gb/ s 25 hybrid lasers 25 hybrid lasers

A future integrated 1 Tb/ s optical link

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46

A future integrated 1 Tb/ s optical link

  • n a single silicon chip
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SLIDE 47
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SLIDE 48
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SLIDE 49

Silicon Photonic Link 50Gb 50Gbps Multichip approach Driver 45 nm CMOS Photonic 90 nm CMOS

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SLIDE 50

Outline Outline

  • Silicon Photonics

Silicon Photonics

  • State of the art

Sili Ph t i f l b hi

  • Silicon Photonics for lab-on-a-chip
  • NanoSilicon photonics
  • Conclusion
  • L. Pavesi

18-11-10

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SLIDE 51

Nanosilicon photonics:

a platform where silicon nanoclusters a platform where silicon nanoclusters enable new functionalities in silicon h t i photonics

  • L. Pavesi

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SLIDE 52

Silicon Nanophotonics Silicon Nanophotonics

  • Confine carriers on nanoscale

Confine carriers on nanoscale dimensions

  • Confine photons on nanoscale

dimensions dimensions

10 μm

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SLIDE 53

Silicon quantum dots Silicon quantum dots

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50 nm

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SLIDE 54

Silicon quantum dots Silicon quantum dots

Eg

c-Si

Eg

c-Si

Bulk Silicon: Indirect band-gap Nanocrystalline-Si: Direct-gap due to QCE Indirect band gap inefficient light emitter g p Q Strong visible light emission

  • L. Pavesi

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SLIDE 55
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SLIDE 56
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SLIDE 57

Purcel effect

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Purcel effect

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SLIDE 58

Integration of microdisk with a waveguide

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SLIDE 59

pHotonics ELectronics functional Integration on CMOS Integration on CMOS

CEIVER RANSC CON TR all SILI

CMOS capacitor based on Si-NC gate

THE

  • L. Pavesi

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25/02/2010 59 Marconi, Anopchenko

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SLIDE 60

Light Emitting Proprieties Light Emitting Proprieties

pHotonics ELectronics functional Integration on CMOS

Light Emitting Proprieties Light Emitting Proprieties

Forward Bias Reverse Bias

Integration on CMOS

CEIVER RANSC

Luminescent

Poly p-type

CON TR

Luminescent Region

Si substrate n-type Al

  • 5 V

all SILI THE

  • L. Pavesi

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SLIDE 61

pHotonics ELectronics functional Integration on CMOS

1

(2 nm SiO2 / 3 nm SRO) 2)

Integration on CMOS

1

Graded energy gap (2 nm SiO2 / 4 nm SRO)

(μW / cm

2

0.1

wer density

0.1 0.2 ficiency (%)

0.01

ptical pow

10

  • 3

10

  • 2

10

  • 1

1

0.0 Power eff Current density (mA / cm

2)

Active n-type poly- silicon p-type silicon +

  • 10
  • 3

10

  • 2

10

  • 1

1 10

1

O Current density (mA / cm

2)

Current density (mA / cm )

Active Si-NC silicon ∼100 nm silicon wafer

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Current density (mA / cm )

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SLIDE 62

pHotonics ELectronics functional Integration on CMOS

Forward Bias Reverse Bias

Integration on CMOS

CEIVER RANSC

Detection R i

Poly p type

CON TR

Region

Si substrate n-type Al Poly p-type

all SILI

Al

THE

  • L. Pavesi

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25/02/2010

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SLIDE 63

pHotonics ELectronics functional Integration on CMOS Integration on CMOS

TTL in TTL in TTL out TTL out

  • L. Pavesi

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25/02/2010 63 Marconi

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SLIDE 64

All optical switching with ili t l silicon nanocrystals

n=n0+n2 I

( )( )

1 2 1 1 cos T ξ ξ ϕ = − − − Δ

α=α0+β I

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SLIDE 65

Comparison to other nonlinear i l materials

Silica

n2= (1.54x10-16) cm2/W [3,4]

Bulk Silicon

n2= (4.5x10-14) cm2/W [3,4]

GaAs

n2= (1.59x10-13) cm2/W [5]

Si-ncs

n2= (2 ÷ 8x10-13) cm2/W [present work]

[3] Handbook of Nonlinear Optics [4] Adair R. et al., Physical Review B, 39, 3337, (February 1989). [5] M. Dinu et al., Applied Physics Letters, 82, 2954 (2003).

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[ ] , pp y , , ( )

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SLIDE 66

All optical switching

  • p ca s

c g

Si nanocrystals activated slot waveguides

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  • A. Martinez et al. Nanoletters (2010)
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SLIDE 67
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  • A. Martinez et al. Nanoletters (2010)
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SLIDE 68

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

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SLIDE 69

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

Photon electron energy conversion 32.9% Unabsorbed energy loss 18.7% Heat loss 46.8% Other losses 1.6%

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SLIDE 70

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

  • L. Pavesi

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SLIDE 71

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

Secondary carrier Secondary carrier generation

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Ryan, Anopchenko, Marconi – APP FBK

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SLIDE 72

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

Silicon nanocrystals

  • L. Pavesi

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Ryan, Anopchenko, Marconi – APP FBK

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SLIDE 73

Improved photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

  • L. Pavesi

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Ryan, Anopchenko, Marconi – APP FBK

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SLIDE 74

0.8 1.0 TSRO RSRO A 0.3 ) ncement (b) PDS-2 0.6 al function ASRO 0.2 nsivity (A/W) ciency enha PR PR 0.2 0.4 Optica 0.1 Photorespon uantum effic PRARC ΔηINT 400 500 600 700 0.0 Wavelength (nm) 0.0 P Internal qu

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A maximum enhancement of the internal quantum efficiency of 14%

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SLIDE 75

Improve photovoltaic efficiency by appl ing no el effects applying novel effects at the limits of light-matter interaction g

Secondary carrier Secondary carrier generation

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Ryan, Anopchenko, Marconi – APP FBK - Minhaz

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SLIDE 76

Cross section of the device

Al (1%Si) 500 nm SiO2 (TEOS) 120 nm Al (1%Si) 500 nm Si Si-

  • rich Oxide 50 nm

rich Oxide 50 nm LPCVD Si3N4 50 nm n-type Poly-Si 30 nm LOCOS 500 nm LOCOS 500 nm P-type Si substrate Al (1%Si) 500 nm Al (1%Si) 500 nm

Device area = 320 μm X 320 μm

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Device area = 320 μm X 320 μm

Ryan, Anopchenko, Marconi – APP FBK - Minhaz

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SLIDE 77

Cross section of the device

Al (1%Si) 500 nm SiO2 (TEOS) 120 nm Al (1%Si) 500 nm Si Si-

  • rich Oxide 50 nm

rich Oxide 50 nm LPCVD Si3N4 50 nm n-type Poly-Si 30 nm LOCOS 500 nm LOCOS 500 nm P-type Si substrate Al (1%Si) 500 nm absorption Al (1%Si) 500 nm

Device area = 320 μm X 320 μm

  • L. Pavesi

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Device area = 320 μm X 320 μm

Ryan, Anopchenko, Marconi – APP FBK - Minhaz

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SLIDE 78

Cross section of the device

Al (1%Si) 500 nm SiO2 (TEOS) 120 nm Al (1%Si) 500 nm Si Si-

  • rich Oxide 50 nm

rich Oxide 50 nm LPCVD Si3N4 50 nm n-type Poly-Si 30 nm LOCOS 500 nm LOCOS 500 nm multiplication P-type Si substrate Al (1%Si) 500 nm absorption Al (1%Si) 500 nm

Device area = 320 μm X 320 μm

  • L. Pavesi

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Device area = 320 μm X 320 μm

Ryan, Anopchenko, Marconi – APP FBK - Minhaz

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SLIDE 79

IR response in Γ3N

1 0

mA)

0 0 0.5 1.0

L - ID) (m

> 1200 nm

1 0

  • 0.5

0.0

urrent (IL

2 0

  • 1.5
  • 1.0

Photo-cu

  • 5
  • 4
  • 3
  • 2
  • 1
  • 2.0

P A li d Bi (V)

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Applied Bias(V)

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SLIDE 80

IR response in Γ3N

1 0

mA)

0 0 0.5 1.0 Voc= 500 mV

L - ID) (m

> 1200 nm

1 0

  • 0.5

0.0

urrent (IL

633 nm

2 0

  • 1.5
  • 1.0

Photo-cu

488 nm

  • 5
  • 4
  • 3
  • 2
  • 1
  • 2.0

P A li d Bi (V)

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Applied Bias(V)

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SLIDE 81

IR response in Γ3N

1 0

mA)

0 0 0.5 1.0 Voc= 500 mV

L - ID) (m

> 1200 nm

1 0

  • 0.5

0.0

rrent (IL

633 nm + 1200 nm

2 0

  • 1.5
  • 1.0

hoto-cu

488 nm + 1200 nm

  • 5
  • 4
  • 3
  • 2
  • 1
  • 2.0

Ph A li d Bi (V)

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Applied Bias(V)

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SLIDE 82

IR response in Γ3N

1 0

mA)

0 0 0.5 1.0 Voc= 500 mV

L - ID) (m

> 1200 nm

1 0

  • 0.5

0.0

rrent (IL

633 nm + 1200 nm

10 %

2 0

  • 1.5
  • 1.0

hoto-cu

488 nm + 1200 nm

  • 5
  • 4
  • 3
  • 2
  • 1
  • 2.0

Ph A li d Bi (V)

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Applied Bias(V)

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SLIDE 83

Solar cell with an internal gain mechanism

Secondary carrier generation ge e at o

  • L. Pavesi

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Ryan, Anopchenko, Marconi – APP FBK - Minhaz

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SLIDE 84

Outline Outline

  • Silicon Photonics

Silicon Photonics

  • State of the art

Sili Ph t i f l b hi

  • Silicon Photonics for lab-on-a-chip
  • NanoSilicon photonics
  • Conclusion
  • L. Pavesi

18-11-10

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SLIDE 85

Conclusions: Conclusions:

  • Silicon photonics is a mature technology

Silicon photonics is a mature technology

  • Silicon photonics allows fabricating thousands
  • f photonic components in a single chip

p p g p

  • Silicon photonics merges electronics and

photonics to enable novel functionalities p

  • Silicon photonics is not only bulk Silicon

(nanosilicon, strained silicon, silicon/germanium, germanium, ….)

  • Silicon photonics is not only optical
  • L. Pavesi

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communication is much more

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SLIDE 86

Bottom line: Bottom line:

  • Each time the market catches size

Each time the market catches size Silicon is the solution

  • If you may want to compete with silicon
  • If you may want to compete with silicon,

do not! Silicon will always make it

  • L. Pavesi

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SLIDE 87
  • L. Pavesi

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SLIDE 88

Acknowledgments Acknowledgments

  • EC: Helios, LIMA, Wadimos, Positive
  • PAT: Gopsi, Naomi
  • MAE: Italy-turkey, mexico, romania
  • HCSC project and OptoI
  • L. Pavesi

18-11-10

  • HCSC project and OptoI
  • ITPAR
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SLIDE 89

Acknowledgments g

  • L. Pavesi

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