Signal Circuit and Transistor Small-Signal Model Lecture notes: - - PowerPoint PPT Presentation

Signal Circuit and Transistor Small-Signal Model

Lecture notes: Sec. 5 Sedra & Smith (6th Ed): Sec. 5.5 & 6.7 Sedra & Smith (5th Ed): Sec. 4.6 & 5.6

• F. Najmabadi, ECE65, Winter 2012

Transistor Amplifier Development

• F. Najmabadi, ECE65, Winter 2012

Bias & Signal

..... : ,...) ( , , , : MOS

r R R r R R D gs GS GS D DS GS

i I i v V v R v V v i v v + = + = + = ..... , : , , , : MOS

R R D D DS GS

I V R I V V ..... , : , , , : MOS

r r D d ds gs

i v R i v v

+

Bias Signal only = (Bias + Signal) - Bias

?

Finding signal circuit elements -- Resistor

• F. Najmabadi, ECE65, Winter 2012

) (

R R R R R R r

I i R RI Ri V v v − = − = − =

Resistor

Voltage Current iv Equation Bias + Signal: vR iR vR = R iR Bias: VR IR VR = R IR Signal: vr = vR − VR ir = iR − IR ??

r r

Ri v =

• A resistor remains as a resistor in the signal circuit.

Finding signal circuit elements -- Capacitor

• F. Najmabadi, ECE65, Winter 2012

dt V v d C dt dV C dt dv C I i i

C C C C C C c

) ( − = − = − =

Capacitor

Voltage Current iv Equation Bias + Signal: vC iC iC = C dvC /dt Bias: VC IC IC = C dVC /dt Signal: vc = vC − VC ic = iC − IC ??

dt dv C i

c c =

• A capacitor remains as a capacitor in the signal circuit.
• Since VC = const., IC = 0 ,

i.e., A capacitor acts as an open circuit for bias circuit.

Finding signal circuit elements – IVS & ICS

• F. Najmabadi, ECE65, Winter 2012

= − = − =

S S IVS IVS ivs

V V V v v

Independent voltage source Voltage Current iv Equation Bias + Signal: vIVS iIVS vIVS = VS = const Bias: VIVS IIVS VIVS = VS = const Signal: vivs = vIVS − VIVS iivs = iIVS − IIVS ??

, ≠ =

ivs ivs

i v

• An independent voltage source becomes a short circuit!
• An independent current source becomes an open circuit!

Similarly:

Exercise: Show that dependent sources remain as dependent sources

Summary of signal circuit elements

• Resistors& capacitors: The Same
• Capacitor act as open circuit in the bias circuit.
• Independent voltage source (e.g., VDD) : Effectively grounded
• Independent current source: Effectively open circuit
• Careful about current mirrors as they are NOT “ideal” current sources (early

effect and/or channel width modulation was ignored!)

• Dependent sources: The Same
• Non-linear Elements:

Different!

• Diodes & transistors ?
• F. Najmabadi, ECE65, Winter 2012

Diode Signal Response

• F. Najmabadi, ECE65, Winter 2012

      −         ×         =         −         + = − = 1 exp exp exp exp : Signal

T d T D s d T D s T d D s D D d

nV v nV V I i nV V I nV v V I I i i

VD ID vd id ?

        = +

T D s D

nV v I i exp : Signal Bias         =

T D s D

nV V I I exp : Bias

vD iD

• A different iv equation!
• iv equation is non-linear!
• Related to bias value, ID!

1 exp       −         × =

T d D d

nV v I i

Diode small-signal model:

• F. Najmabadi, ECE65, Winter 2012

1 exp       −         × =

T d D d

nV v I i

vd id ?

D T D T d D d T d T d T d T d T d T d

v nV I nV v I i nV v nV v nV v nV v nV v nV v         =       −         + × ≈         + ≈         << +         +         + =         1 1 1 exp : 1 If .... ! 2 1 1 exp : Exapnsion Series Taylor

2 d d d D T d

i r i I nV v = =

Formal derivation of small signal model

• F. Najmabadi, ECE65, Winter 2012

2 ) 2 ( ) 1 (

! 2 ) ( ) (

a A a A

v V f v V f ⋅ >> ⋅

) ( ) ( 2

) 2 ( ) 1 ( A A a

V f V f v ⋅ <<

Small signal means:

a A a a

v V f v g i ⋅ = = ) ( ) (

) 1 (

• Signal + Bias for element A (iA, vA) :

iA = f (vA)

• Bias for element A (IA, VA) :

IA = f (VA)

• Signal for element A (ia, va) :

ia = g (va)

( ) ( )

a A A a A a A A A A A A A A A A A

v V f V f v V f v V f V f V v V f V v V f V f v f i ⋅ + ≈ + ⋅ + ⋅ + = + − ⋅ + − ⋅ + = = ) ( ) ( ... ! 2 ) ( ) ( ) ( ... ! 2 ) ( ) ( ) ( ) (

) 1 ( 2 ) 2 ( ) 1 ( 2 ) 2 ( ) 1 (

(Taylor Series Expansion)

a A A A a A

v V f I I i i ⋅ + = + = ) (

) 1 (

Derivation of diode small signal model

• F. Najmabadi, ECE65, Winter 2012

) ( 1

D nV v S D

v f e I i

T D

=         − ⋅ =

T T

nV v S T nV v S

e I nV v f e I v f 1 ) ( 1 ) (

) 1 (

× =         − = 1 ) (

S nV V S nV V S D D

I e I e I V f I

T D T D

− =         − ⋅ = =

d T S D d T nV V S d V v T nV v S d D d

v nV I I v nV e I v nV e I v V f i

T D D T

×       + = ×           ⋅ = ×           ⋅ = × =

=

) (

) 1 ( d T D d T S D d

v nV I v nV I I i ×       ≈ ×       + =

d d d

r v i =

D T d

I nV r ≈

vd id rd = nVT/ID vD iD

Diode can be replaced with a resistor in the signal circuit!

Small signal model vs iv characteristics

• F. Najmabadi, ECE65, Winter 2012

Small signal model is equivalent to approximating the non-liner iv characteristics curve by a line tangent to the iv curve at the bias point

D T D d d D d

I nV V f r v V f i ≈ = × = ) ( 1 ) (

) 1 ( ) 1 (

Derivation of MOS small signal model (1)

• F. Najmabadi, ECE65, Winter 2012
• Signal + Bias for MOS (iD, vGS , vDS) :

iD = f (vGS, vDS), iG = 0

• Bias for MOS (ID, VGS , VDS) :

ID = f (VGS, VDS), IG = 0

• Signal for MOS (id, vgs , vds) :

id = g (vgs , vds), ig = 0 MOS iv equations: iD = f (vGS, vDS) iG = 0

ds V V DS gs V V GS D DS DS V V DS GS GS V V GS DS GS DS GS D d D

v v f v v f I V v v f V v v f V V f v v f i i I

DS GS DS GS DS GS DS GS

× ∂ ∂ + × ∂ ∂ + ≈ + − ⋅ ∂ ∂ + − ⋅ ∂ ∂ + = = = +

, , , ,

... ) ( ) ( ) , ( ) , (

, , ds V V DS gs V V GS d

v v f v v f i

DS GS DS GS

× ∂ ∂ + × ∂ ∂ ≈ (Taylor Series Expansion in 2 variables)

Derivation of MOS small signal model (2)

• F. Najmabadi, ECE65, Winter 2012

ds V V DS gs V V GS d

v v f v v f i

DS GS DS GS

⋅ ∂ ∂ + ⋅ ∂ ∂ =

, ,

) , ( ) 1 ( ) ( 5 .

2 DS GS DS t GS

• x

n D

v v f v V v L W C i = + − = λ µ

m OV D t GS DS t GS

• x

n V V DS t GS

• x

n V V GS

g V I V V V V V L W C v V v L W C v f

DS GS DS GS

≡ = − + − × = + − × = ∂ ∂ 2 ) ( ) 1 ( ) ( 5 . 2 ) 1 )( ( 5 . 2

2 , ,

λ µ λ µ

• D

DS D DS DS t GS

• x

n V V t GS

• x

n V V DS

r I V I V V V V L W C V v L W C v f

DS GS DS GS

1 ) 1 ( ) 1 ( ) 1 ( ) ( 5 . ) ( 5 .

2 , 2 ,

≡ ≈ + = + + − × = − × = ∂ ∂ λ λ λ λ λ µ λ µ λ = + ⋅ =

g

• ds

gs m d

i r v v g i

MOS small signal “circuit” model

• F. Najmabadi, ECE65, Winter 2012

and

• ds

gs m d g

r v v g i i + ⋅ = =

D

• I

r ⋅ ≈ λ 1

OV D m

V I g ⋅ = 2 1 2 2 >> = =

OV A OV

• m

V V V r g λ

Statement of KCL Two elements in parallel Input open circuit

PMOS “circuit” small signal model is identical to NMOS

• F. Najmabadi, ECE65, Winter 2012

=

• PMOS small-signal circuit model is identical to NMOS
• We will use NMOS circuit model for both!
• For both NMOS and PMOS, while iD ≥ 0 and ID ≥ 0, signal quantities: id,

vgs, and vds , can be negative! PMOS* NMOS Exercise: Derive PMOS small signal model (follow derivation of NMOS small-signal model)

Derivation of BJT small signal model (1)

• F. Najmabadi, ECE65, Winter 2012
• Signal + Bias for BJT (iB, iC, vBE , vCE) :

iB = f1 (vBE), iC = f2 (vBE, vCE)

• Bias for BJT (IB, IC, VBE , VCE) :

IB = f1 (VBE), IC = f2 (VBE, VCE)

• Signal for BJT (ib, ic, vbe , vce) :

ib = g1 (vbe), ic = g2 (vbe, vce) BJT iv equations: iB = f1 (vBE) iC = f2 (vBE, vCE)

        + = =

A CE V v s C V v s B

V v e I i e I i

T BE T BE

1 ) / ( β We need to perform Taylor Series Expansion in 2 variables for both iB and iC.

, 1 be V V BE B

v dv df i

CE BE

× ≈

, 2 , 2 ce V V DCE be V V BE C

v v f v v f i

CE BE CE BE

× ∂ ∂ + × ∂ ∂ ≈

Derivation of BJT small signal model (2)

• F. Najmabadi, ECE65, Winter 2012
• ce

be m c be b

r v v g i r v i + = =

π

) ( ) / (

1 BE V v s B

v f e I i

T BE

= = β

be be V V BE B

v r v dv df i

CE BE

× = × ≈

π

1

, 1 π

β r V I e I V dv df

T B V V v s T V V BE

BE T BE CE BE

1 ) / ( 1

, 1

≡ = =

T BE

V V s B

e I I ) / ( β =         + =

A CE V v s C

V v e I i

T BE

1

A CE A V V s A CE V V s C

V V V e I V V e I I

T BE T BE

+ × =         + = 1

m T C V A CE V v T s V V BE

g V I V v e V I dv df

CE V BE T BE CE BE

≡ =         + = 1

,

, 2

• CE

A C V V v A s V V CE

r V V I e V I dv df

CE V BE T BE CE BE

1

,

, 2

≡ + = =

BJT small signal “circuit” model

• F. Najmabadi, ECE65, Winter 2012

C A C CE A

• I

V I V V r ≈ + =

T C m

V I g =

Statement of KCL Two elements in parallel A resistor, rπ , between B & E

• ce

be m c be b

r v v g i r v i + = =

π B T

I V r =

π

We follow S&S: vbe is denoted as vπ Similar to NMOS/PMOS, the small circuit model for a PNP BJT is the same as that of a NPN.

Alternative BJT small signal “circuit” model

• F. Najmabadi, ECE65, Winter 2012

π π π π π

β β β i v r v g r V I I I V I g

m T B B C T C m

= × = = × = = gm Model β ib Model

Summary of transistor small signal models

• F. Najmabadi, ECE65, Winter 2012

D

• OV

D m

I r V I g ⋅ ≈ ⋅ = λ 1 2

• Comparison of MOS and BJT small-signal circuit models:
• 1. MOS has an infinite resistor in the input (vgs) while BJT has a finite resistor, rπ

(typically several kΩ).

• 2. BJT gm is substantially larger than that of a MOS (BJT has a much higher gain).
• 3. ro values are typically similar (10s of kΩ). gm ro >> 1 for both.

NMOS/PMOS

C A

• T

C m B T

I V r r V I g I V r ≈ = = =

π π

β NPN/PNP BJT