Short status update on DCE3 A. Wassatsch Max-Planck Semiconductor - - PowerPoint PPT Presentation

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Short status update on DCE3 A. Wassatsch Max-Planck Semiconductor - - PowerPoint PPT Presentation

Feb 16, 2023 505 likes •700 views

Short status update on DCE3 A. Wassatsch Max-Planck Semiconductor Laboratory Munich (Germany) 13 th International Workshop on DEPFET Detectors and Applications Ringberg 12-15.06.2013 DEPFET A r c t i v e e c t o P D e t i x e l 13

slide-1
SLIDE 1 A c ti ve P i x e l D et ect
  • r

DEPFET

Short status update on DCE3

  • A. Wassatsch

Max-Planck Semiconductor Laboratory Munich (Germany)

13th International Workshop on DEPFET Detectors and Applications Ringberg 12-15.06.2013

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 1

slide-2
SLIDE 2 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test preparation

staggered 30µm bond pad pitch (org. TSMC 65nm lib, recommended by IMEC)

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 2

slide-3
SLIDE 3 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test preparation

staggered 30µm bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 2

slide-4
SLIDE 4 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test preparation

staggered 30µm bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery ball-wetch bond technology needed, contact with different commercial vendors and research institutes

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 2

slide-5
SLIDE 5 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test preparation

staggered 30µm bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery ball-wetch bond technology needed, contact with different commercial vendors and research institutes

  • nly one company left after

different tests for this job (optocap)

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 2

slide-6
SLIDE 6 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

  • ptocap bonding

single layer bond adapter for 2 layer direct bonds

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 3

slide-7
SLIDE 7 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

  • ptocap bonding

single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 3

slide-8
SLIDE 8 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

  • ptocap bonding

single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium

removed during layout postprocessing due to technology concern (width of the isolator path between the pads )

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 3

slide-9
SLIDE 9 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

  • ptocap bonding

single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium

removed during layout postprocessing due to technology concern (width of the isolator path between the pads )

wetch bond foot of outer rows produces shorts to neigbour wires

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 3

slide-10
SLIDE 10 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

  • ptocap bonding

single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium

removed during layout postprocessing due to technology concern (width of the isolator path between the pads )

wetch bond foot of outer rows produces shorts to neigbour wires long wire bond to the outer side pads fixing that problem (alternative 2 layer bond adapter

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 3

slide-11
SLIDE 11 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test results (prelim.)

up to now 6 devices fully bonded

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 4

slide-12
SLIDE 12 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test results (prelim.)

up to now 6 devices fully bonded JTAG on all devices work

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 4

slide-13
SLIDE 13 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test results (prelim.)

up to now 6 devices fully bonded JTAG on all devices work first device (board 3) has multiple substrate contacts (higher power consumtion in the io net), after fixing the bond pressure the following devices doesn’t have these error

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 4

slide-14
SLIDE 14 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

test results (prelim.)

up to now 6 devices fully bonded JTAG on all devices work first device (board 3) has multiple substrate contacts (higher power consumtion in the io net), after fixing the bond pressure the following devices doesn’t have these error all boards has shorts and/or opens in the dhp data input lines

debug via the JTAG io scan cells

  • nly single step modus of the core via JTAG possible (very slow)
  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 4

slide-15
SLIDE 15 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

manpower (?)

currently the dce3 is a single person project (with the exception of bonding and pcb assembly)

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 5

slide-16
SLIDE 16 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

manpower (?)

currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µC, software for test and slow control, ... )

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 5

slide-17
SLIDE 17 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

manpower (?)

currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µC, software for test and slow control, ... )

a single person can’t be an expert in all of these areas

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 5

slide-18
SLIDE 18 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

manpower (?)

currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µC, software for test and slow control, ... )

a single person can’t be an expert in all of these areas

possible tasks for collaborators

DHH serial interface (hardware) ipbus communication interface for slow control (soft+hardware) test firmware development (embedded software) for further dce3 qualification ..

  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 5

slide-19
SLIDE 19 A c ti ve P i x e l D et ect
  • r

DEPFET

status update DCE3 testchip

How to proceed further with the dce3 ?

at a point, where we did not find a fix for the interconnection problem of our asic (bonds), we have to decide how we go on

the working JTAG and the JTAG core test show, that the TSMC technology themselves is under control the hdl algorithm simulations, shows the functionality of the dce3 risk: speed can’t be verified due to the bonding problems, so only syn and p&r results (backanno. simu) for that

submission of the full asic (5k+ nodes) with simple pad configuration (not staggered) end of the year ?

  • ption: bump pads to recover pad area for clustering agents (?)
  • A. Wassatsch (MPI HLL)

Short status update on DCE3 13th Depfet WS 6