Scoreboard R EX R ADD IR Issue ADDR MEM R WB R DIV MULT - - PowerPoint PPT Presentation

Scoreboard Issue ADD MULT DIV

MEM

IR R R R R WB

ADDR

EX R

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Scoreboard Algorithm and Implementation

Concentrate on Data Hazards only

• Array REGBusy[ ] one for each register
• Set to TRUE when an instruction that has that register as destination is issued. Set

to FALSE when the instruction is done and writes result in destination register.

Let f be the id of the FU needed by instruction in IR and d its destination register: if ( REGBusy[d] == FALSE) Issue instruction to Issue Register of FU f; else Stall. if (Issued) Set REGBusy[d] to TRUE; Update Data Flow Graph. Issue Stage: Check instruction in Instruction register; either stall or issue into ISSUE Register

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Assuming Issue Register is not occupied Assuming Issue Register is not occupied

Scoreboard Algorithm and Implementation

Update Data Flow Graph Maintains dependency information between instructions Instruction I is being issued Assume that I reads source registers S, T and writes destination D

• 1. Draw an arrow from instruction I to register D
• 2. Draw either a red or a green arrow from register S to instruction I.

If there is no incoming arrow to S: color outgoing arrow green /* no in-flight writer */ else color it red /* in flight writer */

• 3. Do the same from register T to instruction I.

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Example

Problem of distinguishing a RAW dependency from a WAR dependency A: DIV.D F0, F2, F4 A: MUL.D F6, F0, F8 B: MUL.D F6, F0, F8 B: DIV.D F0, F2, F4 F0 A B F0 A F0 A Issue A Issue B F0 A B Issue A Issue B

B must wait till A writes B must wait till A reads

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Scoreboard Algorithm

Dispatch stage:

• Array of flags FUBusy[ ] one for each functional unit.
• Set to TRUE when an instruction is issued to the FU. Cleared when

instruction is done. For each instruction I in an Issue Register (Assume I reads registers S and T, and writes D)

• If the arrow from S to I and the arrow from T to I are both green
• Read registers S and T
• Remove arrows from S to I and T to I
• Dispatch to FU and set FUBusy[f] to TRUE

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Scoreboard Algorithm

Write stage:

• From among the completed instructions in EX/WB pipeline registers
• Select instruction I that is SAFE-TO-WRITE (I uses FU f and writes to

register d)

• SAFE-TO-WRITE register d is TRUE

if there are no earlier instructions still wanting to read d

• SAFE-TO-WRITE if there are no green arrows out of register d
• Write result to register d
• Remove arrow from I to d
• Change all outgoing arrows from d to green
• FUBusy[f] = FALSE; REGBusy[D] = FALSE;

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Scoreboard Algorithm

Notes:

• An arrow from I to d means instruction I will write register d in the future.
• Since no WAW dependent instructions are issued there will be at most one arrow

into a register at any time.

• In an actual implementation the ID of I is not needed; merely the fact there is a

current writer is sufficient. (Set REGBusy[d] = TRUE)

• A green arrow from S to I means that I wants to read the current value of register S.
• The green informs other instructions not to write to S till I reads it.
• A writer will wait till the arrow is removed to avoid a WAR hazard.
• A red arrow means that I is waiting for the value that the current writer of register S

will produce.

• I will wait till the arrow becomes green to avoid a RAW hazard.
• When the writer updates S it therefore makes every arrow outgoing from S to

green.

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Dataflow graph maintained by the Scoreboard

• An instruction I is identified by the FU it is using
• Writer information (in coming arrows) recorded in bit array

REGBusy[Number of Registers]

• Reader information maintained in a 2-d bit array

DATAFLOW [Number of Registers] [Number of FUs ]

• DATAFLOW[i][j] = 00 if
• REG[i] is not a source register of instruction j
• DATAFLOW[i][j] = 10 (RED arrow from REG[i] to instruction j) if
• REG[i] is a source register of instruction j and
• An in-flight instruction will write to REG[i] (REGBusy[i] is TRUE)
• DATAFLOW[i][j] = 11 (GREEN arrow from REG[i] to instruction j) if
• REG[i] is a source register of instruction j and
• No in-flight instruction will write to REG[i] (REGBusy[i] is FALSE)

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Example: Scoreboard Algorithm

A: LD F6, 0(R2) B: LD F2, 0(R3) C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2) Assume

• ADDR and MEM stages of LD and SD are 1 cycle each
• All FP operations take 4 cycles each
• Assume 1 cycle each for register read (R) and register write (W) stages

Dependencies

• RAW between A,D and A,E (F6)
• RAW between B,C and B,D (F2)
• RAW between C,E (F0)
• WAR between E,F (F6)
• WAW between A,F (F6)

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Scoreboard Issue ADD MULT DIV

MEM

IR R R R R WB

ADDR

ADD R

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Example: Scoreboard Algorithm

A: LD F6, 0(R2) B: LD F2, 0(R3)

B C A

I 1 2 R

B C A

I 1 2 R ADDR 3 C: MULTD F0, F2, F4 I I I I R I

A A F6 F6 B B F2 F2 F6 F6 F2 F2 A A B B F0 F0 C C C C F4 F4 C C

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Example: Scoreboard Algorithm

A: LD F6, 0(R2) B: LD F2, 0(R3) C: MULTD F0, F2, F4 D: SUBD F8, F6, F2

F6 F2

B

F4

C C D

F0

C

B C A

I 1 2 R ADDR 3 I I I I R MEM R R ADDR I I

D

D

4

A D

F8

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Example: Scoreboard Algorithm

A: LD F6, 0(R2) B: LD F2, 0(R3) C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6

F6

B C A

I 1 2 R ADDR 3 MEM 4 I I 5

F2

R R I I

F4

ADDR ADDR R R

D

I I MEM MEM R R R R I I

E

F0

C E D

W W

E D C C B

A IS SAFE TO WRITE A IS SAFE TO WRITE Writes to WB in first half of cycle Writes to WB in first half of cycle A removes its A removes its arrow to F6 arrow to F6 in first half in first half Colors outgoing arrow from F6 Green Colors outgoing arrow from F6 Green Readers read register in second half of Readers read register in second half of cycle cycle E E issues and colors its arrow from issues and colors its arrow from F6 green F6 green in in second half second half

E

F10

D

F8

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Example: Scoreboard Algorithm

B: LD F2, 0(R3) C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

C D B

I 2 3 R ADDR 4 MEM 5 I I 6

F2

R R I I

F4

R R R R

E

I I R R R R R R I I

F

F0

C E D

W W

E D C C

B removes its B removes its arrow to F2 arrow to F2 in first half and in first half and changes C, D outgoing arrows to green changes C, D outgoing arrows to green C C (and also D) sees both its operands ready (and also D) sees both its operands ready (green outgoing arrows). Reads operands (green outgoing arrows). Reads operands and moves to EX stage and moves to EX stage at end of the cycle at end of the cycle

E

F10

D

F8

F

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Example: Scoreboard Algorithm

C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

C E

* *

E

C, D remove outgoing arrows C, D remove outgoing arrows

E

F10

D

F8

F

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Example: Scoreboard Algorithm

C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

C E

* *

E E

F10

D

F8

F

8

• R

R ADDR ADDR * *

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Example: Scoreboard Algorithm

C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

C E

* *

E E

F10

D

F8

F

8

• R

R ADDR ADDR * * 9

• R

R

MEM MEM

* *

F F in in WB stage but in in WB stage but is is NOT SAFE-TO-WRITE NOT SAFE-TO-WRITE due to WAR hazard with E (green arrow out of F6) due to WAR hazard with E (green arrow out of F6)

• R

R

W W

* * 10

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Example: Scoreboard Algorithm

C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

E

* *

E E

F10 F8

F

8

• R

R ADDR ADDR * * 9

• R

R W W * * 10 11 W W R R W W W W

C, D are SAFE-TO-WRITE; C, D are SAFE-TO-WRITE; F is not safe F is not safe Assume Assume C C is chosen to write; is chosen to write; Makes arrow out of F0 green. Makes arrow out of F0 green. E will read its operands in E will read its operands in second half of cycle second half of cycle

D C

• R

R MEM MEM * *

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Example: Scoreboard Algorithm

C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

E

* *

E E

F10 F8

F

8

• R

R ADDR ADDR * * 9

• R

R W W * * 10

• R

R W W * * 11 W W R R W W W W

C, D are SAFE-TO-WRITE; F is not safe C, D are SAFE-TO-WRITE; F is not safe Assume Assume C C is chosen to write; Makes arrow out of F0 is chosen to write; Makes arrow out of F0

• green. E will read its operands in second half of cycle
• green. E will read its operands in second half of cycle

D

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Example: Scoreboard Algorithm

D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

* *

E

F10

D

F8

F

8

• R

R ADDR ADDR * * 9

• R

R MEM MEM * * 10

• R

R WB WB * * 11 WB WB R R WB WB WB WB 12 WB WB DIV DIV WB WB

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Example: Scoreboard Algorithm

D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

F6

D E C

I 3 4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

* *

E

F10 F8

F

8

• R

R ADDR ADDR * * 9

• R

R MEM MEM * * 10

• R

R WB WB * * 11 WB WB R R WB WB WB WB 12 WB WB DIV DIV WB WB 13 DIV DIV WB WB

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Example: Scoreboard Algorithm

E: DIVD F10, F0, F6

F6

D E C

4 R R 5 R 6 I I 7

F2

R R I I

F4

R R R R

F

I I

• R

R R R

F0

* *

E

F10 F8

8

• R

R ADDR ADDR * * 9

• R

R WB WB * * 10

• R

R WB WB * * 11 WB WB R R WB WB WB WB 12 WB WB DIV DIV WB WB 13 DIV DIV WB WB 14 DIV DIV

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Schedule

IF

1

IF I

2

IF I R

3

IF I R A

4

IF I R A M

5

IF I R R M W

6

I R R R W

7

R R + *

8

A R + *

9

M R + * 10 W R + *

11

W R W W

12

W / W

13

W /

14

/

15

/

16

W

17

WAR RAW RAW RAW STRUCT

F E

STRUCT

D C B A

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Example

A: LD F6, 0(R2) B: LD F2, 0(R3) C: MULTD F0, F2, F4 D: SUBD F8, F6, F2 E: DIVD F10, F0, F6 F: LD F6, 8(R2)

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