RTCSA 2015
Responsive and Enforced Interrupt Handling for Real-Time System Virtualization
Hyoseung Kim* Shige Wang† Raj Rajkumar * General Motors R&D
* †
Responsive and Enforced Interrupt Handling for Real-Time System - - PowerPoint PPT Presentation
RTCSA 2015 Responsive and Enforced Interrupt Handling for Real-Time System Virtualization Hyoseung Kim * Shige Wang Raj Rajkumar * * General Motors R&D RTCSA 2015 Workload Consolidation Multi-core CPUs for embedded real-time
RTCSA 2015
* †
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Multi-core CPU Real-Time Hypervisor
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VCPU Task Task Scheduler Task VCPU Task Task PCPU VCPU Scheduler PCPU
VCPU Task Task Scheduler Task VCPU Task Task
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VCPU Scheduler
Task Task Scheduler Task Task Task Interrupt Service Routine VCPU VCPU Guest OS PCPU
Task Task Scheduler Task Task Task Interrupt Service Routine VCPU Guest OS
I/O device (e.g., sensor)
VCPU
Interrupt Service Routine PCPU 5/26
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[1] M. Beckert et al. Sufficient temporal independence and improved interrupt latencies in a real-time hypervisor. In DAC, 2014. [2] J. Kiszka. Towards Linux as a real-time hypervisor. In RTLWS, 2009. [3] A. Lackorzy´nski, A. Warg, M. Volp, and H. H¨artig. Flattening hierarchical scheduling. In EMSOFT, 2012. [4] R. Ma et al. Performance tuning towards a KVM-based embedded real-time virtualization system. J. Inf. Sci. Eng., 29(5):1021–1035, 2013.
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𝑤, 𝑈 𝑗 𝑤)
𝑤: Maximum execution budget
𝑤: Budget replenishment period
𝑗
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𝑞𝑗: (𝐷𝑗 𝑞𝑗, 𝑈 𝑗 𝑞𝑗)
– A signal issued from a hardware device to a PCPU – Handled by the corresponding ISR of the hypervisor
𝑘 𝑤𝑗: (𝐷𝑗 𝑤𝑗, 𝑈 𝑗 𝑤𝑗)
– A software signal from the hypervisor to a VCPU – Handled by the ISR of the guest OS while consuming the VCPU budget
Interrupt storms may happen at runtime Task 𝜐1
Physical Intr. VM Exit
VM Enter Virtual Intr.
VM Exit Task 𝜐2 VM Enter Trap
Interrupt-triggered task 11/26
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Task 𝜐1
Physical Intr. VM Exit
VM Enter Virtual Intr.
VM Exit Task 𝜐2 VM Enter Trap
Interrupt-triggered task
budget depleted Next replenishment Task 𝜐1
Physical Intr. VM Exit
VM Enter Virtual Intr.
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VCPU
Task Task Scheduler Task Task ISR Task
Interrupt-triggered
VCPU
Task Task Scheduler Task Task ISR Task
Pseudo-VCPU Time-triggered Interrupt-triggered Time-triggered
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𝑤, 𝑈 𝑞 𝑤)
𝑞 𝑤
𝑤
Sum of execution times of ISR and interrupt-triggered task Extra budget to reduce blocking time on interrupt handling 15/26
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Task 𝜐1
Physical Intr. VM Exit
VM Enter Virtual Intr.
VM Exit Task 𝜐2 VM Enter Trap
Interrupt-triggered task
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Similar to interrupt handling time in a non-virtualized environment
Delay from VCPU budget depletion Delay from time-triggered tasks Delay from higher-priority interrupt handling 18/26
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vINT has benefits in both task scheduling and interrupt handling 21/26
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vINT shows slightly lower task schedulability But vINT provides significantly higher interrupt service rates 22/26
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1Gbps Ethernet
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