Chapter 4 Interrupts ECE 3120 Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ mmahmoud@tntech.edu
Outline 4 .1 W hat is interrupt? 4.2 Interrupt programming 4.3 IRQ 4.4 Real-time interrupt (RTI)
- An interrupt is an event that requests the CPU to suspend the program execution briefly and run a subroutine called I nterrupt Service Routine ( I SR) . - After executing the ISR, the CPU resumes the program execution from the point it left the program. No command to call the ISR subroutine. Main program The event calls it. org $2000 Entry: ISR movb #10,$1000 The ISR code should movb #15,$1001 . take some necessary movb #20,$1002 . ldaa $1000 actions to respond to . adda $1001 . the event adda $1002 RTI staa $1003 An interrupt means an event has occurred and a relevant action should be taken 4 - 1
- An event can be a signal coming from a device such as sensor, circuit, timer, etc. - Example: A sensor outputs a pulse when a train approaches a crossing – This signal requests interrupt and the MCU runs the relevant ISR that lowers the crossing gate - Serving an interrupt means executing its subroutine (ISR) 4 - 2
Why are interrupts used? Better utilization of CPU Programming big applications To make a delay 1- W ithout interrupts CPU executes some commands so that the execution time = the delay remember Delay_yms Wasting the CPU capability 2- W ith I nterrupt CPU does not waste time CPU Timer It is interrupted every y ms Interrupt every y ms 4 - 3
Write a program to repeatedly turn on a LED for a second Example and turn it off for a second. Also, read from the keypad and display on the LCD. With Interrupt Without Interrupt Main program Begin: ISR Code for Turn a LED on If a LED is on keypad and Turn it off Wait 1 second LCD Else Turn it on Turn a LED off Wait 1 second Called every 1 second Go to begin Because the CPU is so fast, the LEDs, Cannot add the keypad LCD and keypad run smoothly and LCD code because CPU is busy all the time to drive the LED 4 - 4
To detect events (interrupt request signals) 1– Without interrupts (Polling) - To avoid missing an interrupt signal, the CPU must continuously read the sensor pin. The CPU can’t do anything else (e.g., sensing and controlling other devices) 2- Interrupt - The interrupt circuit will notify the CPU when there is an event Polling wastes processor resources checking for events that rarely happen 4 - 5
Without Interrupt With Interrupt Begin: ISR You can write code for If the sensor pin is other 1, lower the gate lower the gate operations Go to Begin Called when CPU continuously checks the the sensor sensor pin because interrupt gives a pulse can happen at any time CPU should not do anything else to avoid missing the event 4 - 6
Outline 4.1 What is interrupt? 4 .2 I nterrupt program m ing 4.3 IRQ 4.4 Real-time interrupt (RTI)
Types of interrupts in HCS12 Maskable interrupts Non-maskable interrupts 1- Maskable interrupts: - The program can ask the CPU to respond or ignore them, i.e., can be enabled and disabled. - CPU does not execute the I SR if the interrupt is disabled - Most of the interrupts are maskable 2- Non-maskable interrupts: - Can’t be disabled or ignored by the CPU . – Used for critical applications, e.g., in case of loss of power, the CPU can save the contents of the registers in a nonvolatile memory when the voltage drops below a threshold. 4 - 7
Enable/ Disable interrupts - Two levels of interrupt enabling capability The CCR 1- Global masking capability - When none of the maskable interrupts are desirable, the processor can disable them by setting the global interrupt mask flag (I in the CCR) - To set flag I ( disable all maskable interrupts): sei or orcc # % 00010000 To clear flag I ( enable all maskable interrupts): cli or andcc # % 11101111 – By default, the I bit is set to 1 during reset. An instruction should be written to clear the I bit to enable maskable interrupts. 2- A local interrupt masking capability Each interrupt source has an enable bit to enable/ disable this interrupt source 4 - 8
Request interrupt The global interrupt flag Different interrupt sources Local interrupt mask flags - If the global interrupt mask flag (I) is disabled, all the interrupts are disabled . - An interrupt is enabled if both the global interrupt m ask flag ( I ) and the local interrupt m ask flags are enabled 4 - 9
4 - 10 Interrupt Flag Bit How to request interrupt from the CPU?
I nterrupt Flag Bit - When an interrupt source wants to request interrupt, it sets a hardware flag (i.e., a flip ‐ flop). - Each interrupt source has its interrupt flag. - The interrupt flag bit should be cleared when the interrupt is served. - As long as this bit is set, there is an interrupt that is not served yet. 4 - 11
I SR starting address - To serve an interrupt, the CPU needs to know the starting address of the interrupt service routine (ISR). This address is called I nterrupt Vector - The interrupt vector of each interrupt source should be stored at a predefined fixed m em ory location called Vector address. When IRQ requests $FF80 $4103 -- interrupt, the CPU fetches --- the ISR starting address $ 4104 -- from $FFF2: $FFF3 $FFF2 41 --- Vector address: $FFF2: $FFF3 $FFF3 03 --- Interrupt vector: $4103 -- The IRQ ISR --- We cannot change $FFF2: $FFF3 RTI $FFFF but we can change 4103 - To set up IRQ interrupt, the programmer should Org $FFF2 store the ISR starting address at the predefined dc.w IRQ_ISR location. 4 - 12
Priority 4 - 13 ATD: Analog to digital
4 - 14 Priority
Interrupt priority – It is possible that several interrupts would be pending at the same time - The CPU cannot serve more than one interrupt at the same time. - CPU has to decide which interrupt to serve first the interrupts should be prioritized. - The ISR of the highest priority interrupt is executed first - In table 6.1, the interrupt that has higher vector address has higher priority , e.g., / IRQ has the higher priority than timer channel 0. - However, we can raise one of the maskable interrupts to the highest level so that it can get quicker service. - To do that, write the low byte of the vector address to the highest priority interrupt register (HPRIO). Raise the timer channel 7 interrupt to the highest priority. The relative priorities of the other interrupts movb # $E0,HPRIO remain the same The address of HPRIO is defined in “mc9s12dg256.inc” file 4 - 15
A complete interrupt service cycle The complete story 1. When an event occurs, a flag bit should be set to interrupt the CPU. 2. This interrupt request is served if: - (1) I bit and local interrupt enable bit are enabled in case of maskable interrupts (2) It is the only interrupt or the highest priority interrupt if there are several interrupts pending for service Stack on entry of an ISR SP CCR SP+ 1 3. To serve the interrupt, the CPU A SP+ 2 B automatically pushes all the registers SP+ 3 X high byte (except SP) on the stack (9 bytes total). X low byte This includes the return address stored in SP+ 5 Y high byte PC and CCR register Y low byte SP+ 7 do not mess up stack! PC high byte PC low byte 4 - 16
5. The CPU prevents further interrupts from occurring till the ISR is done by setting the I bit. Nested interrupts are not allowed. 6. Resolve the interrupt vector and transfer control to the interrupt service routine (ISR). PC = the ISR starting address 7. Cancel the interrupt request by clearing the interrupt flag. Without this step the interrupt will be executed over and over again and the main program would never execute again 8- Execute the ISR instructions. Use all the CPU registers w ithout fear of interfering w ith the m ain program , but for memory locations, it is the programmer’s responsibility to ensure that the ISR does not change memory locations used by the main program 9. The last instruction in an ISR is always “RTI” (return from interrupt) - RTI retrieves the registers’ original values before executing the interrupt from the stack. Enable I bit and return back to the main program 4 - 17
Interrupt programming 1- Main program 1.1 Initializing the interrupt vector 1.2 Configuration, e.g., respond to level or falling edge, set time out, etc. 1.3 Enable interrupt: Global and local - It is important not to enable the interrupts before the initialization is done 2- The interrupt subroutine 2.1 Clear the interrupt flag bit 2.2 Must end with RTI instruction 4 - 18
Outline 4.1 What is interrupt? 4.2 Interrupt programming 4 .3 I RQ 4.4 Real-time interrupt (RTI)
/ IRQ Pin Interrupt - Port E pin 1 (PE1) - The only external maskable interrupt for the HCS12. /IRQ 4 - 19
IRQ Interrupt programming 1- Main program 1.1 Initializing the interrupt vector Org $FFF2 IRQ_ISR is the name of the routine dc.w IRQ_ISR 1.2 Configuration When does the interrupt occur ? Low level (/ IRQ = 0) or falling edge (/ IRQ transfers from 1 to 0). 1.3 Enable local interrupt 1.2 and 1.3 are done by setting the interrupt control register (INTCR) that has the address $001E. 4 - 20
- Local enable bit : IRQEN bit 6 of the IRQCR register. IRQEN = 1 enabled and IRQEN = 0 disabled - The triggering m ethod : IRQE = 0 respond to low level, and IRQE = 1 responds to falling edge I NTCR register movb #$40,INTCR ; enable IRQ interrupt and respond to low level edge 4 - 21
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