Packet Striping Hari Adiseshu@Washington University 1
Reliable and Scalable Packet Striping Hari Adiseshu Guru Parulkar - - PowerPoint PPT Presentation
Reliable and Scalable Packet Striping Hari Adiseshu Guru Parulkar - - PowerPoint PPT Presentation
Reliable and Scalable Packet Striping Hari Adiseshu Guru Parulkar George Varghese Washington University in St. Louis 1 Hari Adiseshu@Washington University Packet Striping Introduction u Packet Striping * using multiple links as a single
Packet Striping Hari Adiseshu@Washington University 2
Introduction
u Packet Striping
* using multiple links as a single logical link
u Used for performance or cost reasons
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Current Striping Techniques
u Usually at the physical level (Inverse
Multiplexing)
u Physical level striping has drawbacks u Wanted: packet striping at a logical level u Multilink PPP provides framing, not load
sharing
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Packet Striping Reference Model
Channel Resequencing Algorithm Channel Striping Algorithm
Sender Receiver Desirable properties: Desirable properties: Desirable properties: Load Sharing Load Sharing Load Sharing FIFO delivery FIFO delivery FIFO delivery Assume: All Channels are FIFO Assume: All Channels are FIFO Assume: All Channels are FIFO
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Overview of Talk
u How to achieve load sharing u How to achieve FIFO delivery u How to recover from packet loss u Experimental results
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Contributions
u Provide a transformation of a class of fair
queuing algorithms into striping algorithms providing load sharing
u Provide a specific instance of such a fair
queuing algorithm
u Show how to achieve Quasi-FIFO delivery
at the receiver
u Show how to recover from packet loss
through periodic marker packets
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RR Striping Algorithm 100 1 100 2 100 3 100 4 100 1 100 2 100 4 100 3 Equal Sized Packets
Round Robin Striping
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RR Striping Algorithm 200 1 100 2 200 3 100 4 200 1 100 2 100 4 200 3 No Load Sharing with unequal sized packets
Round Robin Striping
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Causal Fair Queuing Algorithm
Use function f(s) to select queue Transmit packet p at head of queue Update state using function g(s, p) f(s)
Load Sharing Algorithm
f(s)
CFQ and Load Sharing
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Load Sharing
u CFQ algorithms - FQ algorithm in which
queue to be served depends only on packets sent so far
u CFQ algorithms can be modeled as repeated
applications of two functions
u Theorem: Causal FQ algorithms can be
transformed into load sharing algorithms with the same fairness properties
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Surplus Round Robin (SRR)
u Example of a CFQ algorithm u Each input queue associated with a
Quantum and a Deficit Counter (DC)
u Queues served in round robin order u At each visit to a queue, DC is incremented
by Quantum
u Each queue served as long as DC is
positive
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SRR CFQ Algorithm
400 7 250 1 300 2 400 5 200 6 300 3 Output Channel 400 5 200 6 300 2
DC1 = -50 DC2 = -100 DC1 = 500 DC2 = 500
Round 1 400 7 300 3 150 4
DC1 = 0 DC2 = 0 DC1 = 450 DC2 = 400
Round 2 Queue 1 Queue 2
DC1 = 0 DC2 = 0
Initialization
Quantum = 500
SRR Causal Fair Queuing
250 1 150 4
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SRR Transform Algorithm
400 7 250 1 300 2 200 3 400 4 300 5 Input Queue 400 7 300 5 150 6
DC1 = 0 DC2 = 0 DC1 = 450 DC2 = 400
Round 2 Output Channel 1 Output Channel 2
DC1 = 0 DC2 = 0
Initialization
Quantum = 500
SRR Transform for Load Sharing
200 3 400 4 300 2
DC1 = -50 DC2 = -100 DC1 = 500 DC2 = -500
Round 1 250 1 150 6
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SRR Results
u SRR transform provides load sharing if the
Quantum associated with each channel is proportion to its capacity, and is greater than the maximum packet size
u K rounds after initialization, the difference
between data actually sent over a channel i and the amount that actually should have been sent is bounded by Quantumi
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Contributions
u Provide a transformation of a class of fair
queuing algorithms into striping algorithms providing load sharing
u Provide a specific instance of such a fair
queuing algorithm
u Show how to achieve Quasi-FIFO delivery
at the receiver
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FIFO delivery
u Guaranteed FIFO - add sequence number to
packets
* not always possible, e.g.. ATM cells, transparent Ethernet striping
u Quasi-FIFO - FIFO in the absence of
packet loss
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100 3 100 2 100 4 100 1 Time Axis Physical Reception 100 3 100 2 100 4 100 1 Time Axis Logical Reception
Logical Reception
u Receiver
Buffering
u Receiver
simulation
- f the
sending algorithm
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SRR CFQ Algorithm SRR Transform Algorithm
Quasi-FIFO reception using SRR
Sender Sender Receiver Receiver
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Quasi-FIFO result
u The combination of a transformed version
- f a CFQ algorithm at the sender, and the
CFQ algorithm at the receiver provides Quasi-FIFO delivery
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SRR Transform Algorithm
Sender
100 6 100 4 100 2 100 5 100 3 100 1 100 3 100 1 100 2 100 4 100 5 100 6
Input Queue Input Queue Channel 1 Channel 1 Channel 2 Channel 2
Effect of Packet Loss
SRR CFQ Algorithm
100 3 100 1 100 2 100 4 100 5 100 6
Output Queue Output Queue Receiver
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Effect of Packet Loss
SRR Transform Algorithm
Sender
100 12 100 10 100 8 100 11 100 9 100 7 100 9 100 7 100 8 100 10 100 11 100 12
Input Queue Input Queue Channel 1 Channel 1 Channel 2 Channel 2
Effect of Packet Loss
SRR CFQ Algorithm
100 11 100 9 100 8 100 10
Output Queue Output Queue
Packet 7 is lost Packet 7 is lost Buffered Buffered Buffered
Receiver
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Recovery from Packet Loss
u Synchronization depends on shared state between sender
and receiver
u On packet loss, the shared state is lost u Solution: propagate state periodically from the sender to
the receiver
u For the specific case of SRR algorithm, state consists of
Round Number, and Deficit Counter values for each link
u Periodically propagate these values to the receiver using
marker packets
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Sync Recovery
SRR Transform Algorithm
Sender
100 18 100 16 100 14 100 17 100 15 100 13 100 15 100 13 100 14 100 16 100 17 100 18
Input Queue Input Queue Channel 1 Channel 1 Channel 2 Channel 2
SRR CFQ Algorithm
100 15 100 13 100 14 100 16 100 17 100 18
Output Queue Output Queue
G=7M
Marker causes receiver to skip channel Marker causes receiver to skip channel
100 12 100 12
Buffered Buffered Buffered
Receiver
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IP IP IP IP Convergence Convergence Layer Layer Data Link Data Link Interface Interface strIPe strIPe IP IP Convergence Convergence Layer Layer Data Link Data Link Interface Interface
strIPe layer
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Ethernet Ethernet ATM ATM
Experimental Setup
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NetBSD Implementation
2 4 6 8 10 12 14 16 18 20 10 20 30
ATM Channel Capacity (Mbps) Application Level Throughput (Mbps)
Sum of Ethernet and ATM Throughputs SRR, logical reception SRR, no logical reception GRR, logical reception GRR, no logical reception RR, logical reception RR, no logical reception Contributions
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Experimental Results
u Throughput with SRR matched aggregate
throughput
u Throughput more with resequencing u Throughput of SRR greater than other
variants
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