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Mar 01, 2024 120 likes β€’287 views

Reli liability-Aware Scheduling on Heterogeneous Multicore Processors Ajeya Naithani Stijn Eyerman Lieven Eeckhout Ghent University, Belgium Intel, Belgium Ghent University, Belgium HPCA 2017 Motivation Wide use of

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SLIDE 1

Reli liability-Aware Scheduling on Heterogeneous Multicore Processors

Ajeya Naithani Stijn Eyerman Lieven Eeckhout Ghent University, Belgium Intel, Belgium Ghent University, Belgium HPCA 2017

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SLIDE 2

Motivation

  • Wide use of Heterogeneous Chip Multi-Processors (HCMPs) in mobile SoCs
  • e.g., ARM’s big.LITTLE, Nvidia’s Tegra

Fast More Transistors! Simple Longer Execution!

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SLIDE 3

Goal

  • Increasing robustness of HCMPs against soft errors
  • Reliability-aware scheduling of HCMPs based on:
  • Core type
  • Workload

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SLIDE 4

Terminology

  • ACE bit: Architecturally Correct Execution bit
  • ABC: ACE Bit Count
  • AVF: Architectural Vulnerability Factor
  • IFR: Intrinsic Fault Rate
  • SER: Soft Error Rate

T Time

ABC ACE Bit π΅π‘ŠπΊ = 𝐡𝐢𝐷 π‘ˆπ‘π‘’π‘π‘š 𝐢𝑗𝑒 π·π‘π‘£π‘œπ‘’ 𝑇𝐹𝑆 = 𝐡𝐢𝐷 π‘ˆ Γ— 𝐽𝐺𝑆

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SLIDE 5

Reliability-Aware Scheduling

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  • Requires a metric for system-wide reliability

𝑇𝑧𝑑𝑒𝑓𝑛_𝑇𝐹𝑆 = ෍

𝑗=1 π‘œ

𝑇𝐹𝑆𝑗 Applications may slow down!

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SLIDE 6
  • Reliability Metric: System-level Soft Error Rate(SSER)

𝑇𝑇𝐹𝑆 = ෍

𝑗=1 π‘œ

π‘₯𝑇𝐹𝑆𝑗

  • Weighted SER:

π‘₯𝑇𝐹𝑆 = 𝐡𝐢𝐷 π‘ˆ Γ— π‘ˆ π‘ˆπ‘ π‘“π‘” Γ— 𝐽𝐺𝑆 = 𝐡𝐢𝐷 π‘ˆπ‘ π‘“π‘” Γ— 𝐽𝐺𝑆

Reliability-Aware Scheduling

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SLIDE 7

Reliability-Aware Scheduling

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Start

Sampling Data per Application: 1. ABC on Different Cores 2. Performance on Different Cores

Sampling data up to date? No Yes Update all the possible wSERs Switch couple of apps which decreases SSER Record performance and ABC for each application Update sampling data

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SLIDE 8

Hardware Overhead

  • Profiled structures:
  • ROB
  • Issue queue
  • Load/store queue
  • Physical output registers
  • Functional units
  • Total hardware overhead:
  • 904 bytes per big core
  • 67 bytes per little core
  • Approximation: Only profile ROB β†’ HW overhead: 296 bytes per big core

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SLIDE 9

Evaluation

  • Three schedulers:
  • Random
  • Reliability-optimized
  • Performance-optimized
  • Benchmark suite
  • SPEC CPU2006

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SLIDE 10

Application Characteristics

[Fig. 1 in the paper]

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SLIDE 11

Results – Symmetric HCMP (2B2S)

[Fig. 6 in the paper] 32% improvement over random scheduling 25.4% improvement over performance-optimized scheduling Same as random scheduling 6.3% degradation over performance-optimized scheduling

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SLIDE 12

Results – Asymmetric HCMP

[Fig. 8 in the paper]

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SLIDE 13

Results – Workload Categories

[Fig. 7 in the paper]

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SLIDE 14

Results – Approximate Profiling

[Modified version of Fig. 10 in the paper]

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SLIDE 15

Conclusion

  • Applications and cores β†’ Different vulnerability characteristics
  • Reliability-aware scheduling:
  • System reliability 25.4% ↑
  • Performance 6.3% ↓
  • The proposed scheduler is robust across:
  • Core configurations
  • Workload types

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SLIDE 16

Discussion Points

  • HCMPs are mainly used in mobile SoCs, while the evaluated benchmarks target

server/desktop processors. Is the sampling method actually applicable to mobile applications, which are heavily I/O based?

  • The scheduling is implemented in software. Is it efficient in a battery-

constrained platform?

  • What if the number of applications is more than the number of cores?

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