Multicore Processors Raul Queiroz Feitosa Parts of these slides are from the support material provided by W. Stallings
Objective Objective “This chapter provides an overview of multicore systems”. Stallings 2 Multicore Computers
Outline Outline Hardware Performance Issues Software Performance Issues Multicore Organizations Intel Core Architecture 3 Multicore Computers
Hardware performance issues Chip Density Microprocessors performance increase due to Pipelining Superscalar a) Improved organization, e.g., Multithreading … b) Increased clock frequency both made possible by 1. increasing chip density! By 2018 → 30 trillion transistors on 300mm 2 die. 4 Multicore Computers
Hardware performance issues Chip Density Microprocessors performance increase in due to Pipelining Superscalar a) Improved organization, e.g., Multithreading … b) Increased clock frequency both made possible by 1. increasing chip density! By 2015 → 100 billion transistors on 300mm 2 die. 5 Multicore Computers Source: IEEE Spectrum, 2017
Pollack’s Rule “performance is roughly proportional to square root of increase in complexity” . 2. Diminishing gains with complexity increase! Complexity Power Performance Single thread computer 1 1 1 4 4 2 25 25 5 Four small cores Complexity Power Performance 4 1 4 1 4 6 Multicore Computers
Hardware performance issues Source: Henk Poleyy, 2014 7 Multicore Computers
Hardware performance issues Source: Henk Poleyy, 2014
Hardware performance issues Power 3. Power requirements grow exponentially with chip density and clock frequency! 9 Multicore Computers
Hardware performance issues Increased Complexity 4. Memory transistors have a power density an order of magnitude lower than that of logic. 10 Multicore Computers
Outline Outline Hardware Performance Issues Software Performance Issues Multicore Organizations Intel Core Architecture 11 Multicore Computers
Software Performance Issues small amounts of serial code impact performance According to Amdahl’s law time to execute program on a single processor 1 Speedup f time to execute program on N parallel processors 1 f N where f is the fraction of code infinitely parallelizable with no schedule overhead. 12 Multicore Computers
Software Performance Issues Small amounts of serial code impact performance due to communication, distribution of work and cache coherence overheads percentage of sequential code 13 Multicore Computers
Software Performance Issues More recently software engineers have developed applications that effectively exploit multiprocessor architecture, e. g., database applications. 5. New applications exploit multiprocessor architecture! 14 Multicore Computers
Outline Outline Hardware Performance Issues Software Performance Issues Multicore Organization Intel Core Architecture 15 Multicore Computers
Multicore Organization In view of: Increasing chip density. 1. Diminishing gains with complexity increase. 2. Power requirements grow exponentially with chip density 3. and clock frequency. Memory transistors have a power density one order of 4. magnitude lower than that of logic. Applications, which exploit multiprocessor architecture. 5. What to do with extra transistors made available by the semiconductor industry? 16 Multicore Computers
Multicore Organization What to do with extra transistors made available by the semiconductor industry? Reduce complexity, so that multiple complete processors fit in a single chip Reduce clock frequency and increase the proportion of chip occupied by cache to reduce power requirements 17 Multicore Computers
Multicore Organization Main variable in a multicore organization: Number of core processors on chip Number of levels of cache on chip Amount of shared cache 18 Multicore Computers
Multicore Organization Alternatives Dedicated L1Cache (ARM 11 MPCore) 19 Multicore Computers
Multicore Organization Alternatives Dedicated L1Cache (AMD Opteron) 20 Multicore Computers
Multicore Organization Alternatives Shared L2 Cache (Intel Core Duo) 21 Multicore Computers
Multicore Organization Alternatives Shared L3 Cache (Intel Core i7) 22 Multicore Computers
Private × shared L2 Cache Advantages of shared L2 Cache Constructive interference reduces overall miss rate Data shared by multiple cores not replicated at cache level With proper frame replacement algorithms mean amount of shared cache dedicated to each core is dynamic Threads with less locality can have more cache Easy inter-process communication through shared memory Cache coherency confined to L1 Advantages of private L2 Cache Dedicated L2 cache gives each core more rapid access Shared L3 cache may also improve performance 23 Multicore Computers
Outline Outline Hardware Performance Issues Software Performance Issues Multicore Organization Intel Core Architecture 24 Multicore Computers
Intel i3, i5, i7, i9 Source: Intel 10 th Gen Intel Core Desktop Processors 25 Multicore Computers
Multicore Processors END 26 Multicore Computers
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