SLIDE 1
Multicore Processors
Raul Queiroz Feitosa
Parts of these slides are from the support material provided by W. Stallings
Objective
“This chapter provides an overview of multicore systems”. Stallings
Objective
Multicore Processors Raul Queiroz Feitosa Parts of these slides are - - PowerPoint PPT Presentation
Multicore Processors Raul Queiroz Feitosa Parts of these slides are - - PowerPoint PPT Presentation
Multicore Processors Raul Queiroz Feitosa Parts of these slides are from the support material provided by W. Stallings Objective Objective This chapter provides an overview of multicore systems. Stallings 2 Multicore Computers
SLIDE 2 Multicore Computers 2
SLIDE 3 Multicore Computers 3
Outline
Hardware Performance Issues Software Performance Issues Multicore Organizations Intel Core Architecture
Outline
SLIDE 4 Multicore Computers 4
Hardware performance issues
Chip Density
Microprocessors performance increase due to
a) Improved organization, e.g., b) Increased clock frequency
both made possible by 1. increasing chip density!
Pipelining Superscalar Multithreading …By 2018 → 30 trillion transistors on 300mm2 die.
SLIDE 5 Multicore Computers 5
Hardware performance issues
Chip Density
Microprocessors performance increase in due to
a) Improved organization, e.g., b) Increased clock frequency
both made possible by 1. increasing chip density!
Pipelining Superscalar Multithreading …By 2015 → 100 billion transistors on 300mm2 die.
Source: IEEE Spectrum, 2017 SLIDE 6
“performance is roughly proportional to square root of increase in complexity” . Single thread computer Four small cores
Pollack’s Rule
Complexity Power Performance 1 1 1 4 4 2 25 25 5
Multicore Computers 6Complexity Power Performance 41 41 4
- 2. Diminishing gains with complexity increase!
SLIDE 7
Hardware performance issues
Multicore Computers 7 Source: Henk Poleyy, 2014 SLIDE 8
Hardware performance issues
Source: Henk Poleyy, 2014 SLIDE 9 Multicore Computers 9
Hardware performance issues
Power
- 3. Power requirements grow exponentially with
chip density and clock frequency!
SLIDE 10 Multicore Computers 10
Hardware performance issues
Increased Complexity
- 4. Memory transistors have a power density an
- rder of magnitude lower than that of logic.
SLIDE 11 Multicore Computers 11
Outline
Hardware Performance Issues Software Performance Issues Multicore Organizations Intel Core Architecture
Outline
SLIDE 12 Multicore Computers 12
Software Performance Issues
small amounts of serial code impact performance
According to Amdahl’s law
where f is the fraction of code infinitely parallelizable with no schedule
- verhead.
N f f N 1 1 processors parallel
- n
program execute to time processor single a
- n
program execute to time Speedup
SLIDE 13 Multicore Computers 13
Software Performance Issues
Small amounts of serial code impact performance due to communication, distribution of work and cache coherence overheads
percentage of sequential code SLIDE 14 Multicore Computers 14
Software Performance Issues
More recently software engineers have developed applications that effectively exploit multiprocessor architecture, e. g., database applications.
- 5. New applications exploit multiprocessor architecture!
SLIDE 15 Multicore Computers 15
Outline
Hardware Performance Issues Software Performance Issues Multicore Organization Intel Core Architecture
Outline
SLIDE 16 Multicore Computers 16
Multicore Organization
In view of:
1.
Increasing chip density.
2.
Diminishing gains with complexity increase.
3.
Power requirements grow exponentially with chip density and clock frequency.
4.
Memory transistors have a power density one order of magnitude lower than that of logic.
5.
Applications, which exploit multiprocessor architecture.
What to do with extra transistors made available by the semiconductor industry?
SLIDE 17 Multicore Computers 17
Multicore Organization
What to do with extra transistors made available by the semiconductor industry?
Reduce complexity, so that multiple complete processors
fit in a single chip
Reduce clock frequency and increase the proportion of
chip occupied by cache to reduce power requirements
SLIDE 18 Multicore Computers 18
Multicore Organization
Main variable in a multicore organization:
Number of core processors on chip Number of levels of cache on chip Amount of shared cache
SLIDE 19
Multicore Organization Alternatives
Dedicated L1Cache (ARM 11 MPCore)
Multicore Computers 19 SLIDE 20
Multicore Organization Alternatives
Dedicated L1Cache (AMD Opteron)
Multicore Computers 20 SLIDE 21
Multicore Organization Alternatives
Shared L2 Cache (Intel Core Duo)
Multicore Computers 21 SLIDE 22
Multicore Organization Alternatives
Shared L3 Cache (Intel Core i7)
Multicore Computers 22 SLIDE 23 Multicore Computers 23
Private × shared L2 Cache
Advantages of shared L2 Cache
Constructive interference reduces overall miss rate Data shared by multiple cores not replicated at cache level With proper frame replacement algorithms mean amount of shared
cache dedicated to each core is dynamic
Threads with less locality can have more cache Easy inter-process communication through shared memory Cache coherency confined to L1
Advantages of private L2 Cache
Dedicated L2 cache gives each core more rapid access
Shared L3 cache may also improve performance
SLIDE 24 Multicore Computers 24
Outline
Hardware Performance Issues Software Performance Issues Multicore Organization Intel Core Architecture
Outline
SLIDE 25
Intel i3, i5, i7, i9
Multicore Computers 25 Source: Intel 10th Gen Intel Core Desktop Processors SLIDE 26 Multicore Computers 26
Multicore Processors