Efficient Execution of Dependent Tasks on Many-Core Processors - PowerPoint PPT Presentation

Efficient Execution of Dependent Tasks on Many-Core Processors Hamza Rihani, Claire Maiza, Matthieu Moy Univ. Grenoble Alpes Verimag RTSOPS 2016, July 5, 2016

Context PE PE PE PE High Level Language PE PE PE PE i 1 o τ 1 τ 2 τ 3 PE PE PE PE τ 4 i 2 τ 5 τ 6 PE PE PE PE ◦ Hard real-time systems ◦ Dependent tasks statically scheduled, on a many-core processor ! Unpredictable delays due to shared resource interference 2 ,

Context PE PE PE PE High Level Language PE PE PE PE i 1 o τ 1 τ 2 τ 3 PE PE PE PE τ 4 i 2 τ 5 τ 6 PE PE PE PE ◦ Hard real-time systems ◦ Dependent tasks statically scheduled, on a many-core processor ! Unpredictable delays due to shared resource interference Use tightly estimated upper bounds on delays 2 ,

Context PE PE PE PE High Level Language PE PE PE PE i 1 o τ 1 τ 2 τ 3 PE PE PE PE τ 4 i 2 τ 5 τ 6 PE PE PE PE ◦ Hard real-time systems ◦ Dependent tasks statically scheduled, on a many-core processor ! Unpredictable delays due to shared resource interference Use tightly estimated upper bounds on delays Connect existing approaches for an optimally efficient execution 2 ,

Outline 1 Solved Problems Code Generation Task Mapping WCRT Analysis 2 Toward a Solution 3 The Open Problem 3 ,

Solved Problems High-level Timing models Program Code Generation (static analysis) Probabilistic Models Local WCRT Tasks Analysis + Dependencies Tasks WCRT Static + Mapping/Scheduling WC Access Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary 4 ,

Solved Problems High-level Program Code Generation Tasks + Dependencies Static Mapping/Scheduling Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary 4 ,

Solved Problems: Code Generation i 1 o τ 1 τ 2 τ 3 High-level Program Code Generation τ 4 i 2 Tasks τ 5 τ 6 + Dependencies Static Mapping/Scheduling Outputs ◦ Task binaries Mapping WCRT with Interferences Execution ◦ Task dependency graph Order Release ◦ Execution models: (Pellizzoni et al.[6]) Dates Binary Generation ◦ Single phase execution ◦ acquisition, execution, replication phases Executable Binary 5 ,

Solved Problems: Task Mapping/Scheduling τ 4 τ 5 PE 2 wcrt 4 wcrt 5 High-level Program Code Generation τ 3 τ 2 PE 1 wcrt 3 wcrt 2 Tasks + Dependencies τ 0 τ 1 wcrt 0 wcrt 1 PE 0 Static Mapping/Scheduling Mapping (*)wcrt x : safe WCRT WCRT with Execution Interferences Order Release Dates Binary Generation ◦ Respect the dependency constraints Executable Binary ◦ Optimize the overall response time Puffitsch et al. 2013 [7], Giannopoulou et al. 2013 [4], Walter et al. 2015 [8] 6 ,

Solved Problems: WCRT Analysis τ 4 τ 5 wcrt + wcrt + PE 2 4 5 High-level Program Code Generation τ 3 τ 2 wcrt + wcrt + PE 1 3 2 Tasks + Dependencies τ 0 τ 1 wcrt + wcrt + PE 0 Static 0 1 Mapping/Scheduling Mapping WCRT with (*)wcrt + x : refined WCRT Interferences Execution Order Release Dates Binary Generation ◦ Take the interference into account Executable Binary ◦ Update the release times 7 ,

Solved Problems: WCRT Analysis τ 4 τ 5 wcrt + wcrt + PE 2 4 5 High-level Program Code Generation τ 3 τ 2 wcrt + wcrt + PE 1 3 2 Tasks + Dependencies τ 0 τ 1 wcrt + wcrt + PE 0 Static 0 1 Mapping/Scheduling Mapping WCRT with (*)wcrt + x : refined WCRT Interferences Execution Order Release Dates Binary Generation ◦ Take the interference into account Executable Binary ◦ Update the release times The overall response time may not be optimal 7 ,

Toward a Solution High-level Program Code Generation Tasks + Dependencies Static Mapping/Scheduling Mapping WCRT with Interferences Execution Order Release Dates Provide new timing information to the Binary Generation mapping/Scheduling analysis Executable Binary 8 ,

Toward a Solution ◦ Mapping/Scheduling: ◦ Taking into account new timing information ◦ Co-schedule communications and High-level Program Code Generation computations (Melani et al. 2015 [5]) ◦ Clustering non-interfering tasks Tasks (Choi et al. 2016 [2]) + Dependencies Static Mapping/Scheduling Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary 9 ,

Toward a Solution ◦ Mapping/Scheduling: ◦ Taking into account new timing information ◦ Co-schedule communications and High-level Program Code Generation computations (Melani et al. 2015 [5]) ◦ Clustering non-interfering tasks Tasks (Choi et al. 2016 [2]) + Dependencies ◦ WCRT Analysis: Static ◦ Trade-off: run-time/ pessimism Mapping/Scheduling Altmeyer et al. 2015 [1], Dasari et al. 2015[3] Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary 9 ,

Toward a Solution ◦ Mapping/Scheduling: ◦ Taking into account new timing information ◦ Co-schedule communications and High-level Program Code Generation computations (Melani et al. 2015 [5]) ◦ Clustering non-interfering tasks Tasks (Choi et al. 2016 [2]) + Dependencies ◦ WCRT Analysis: Static ◦ Trade-off: run-time/ pessimism Mapping/Scheduling Altmeyer et al. 2015 [1], Dasari et al. 2015[3] Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary Fixed-point search algorithms 9 ,

The Open Problem Iterate until an optimal solution is found What about convergence? High-level Program Code Generation Tasks + Dependencies Static Mapping/Scheduling Mapping WCRT with Interferences Execution Order Release Dates Binary Generation Executable Binary 10,

The Open Problem Iterate until an optimal solution is found What about convergence? High-level Program Code Generation Tasks + Dependencies Suboptimal: Static Mapping/Scheduling ◦ Compute several solutions, Mapping WCRT with choose the best one Interferences Execution Order ◦ How many iterations? Release Dates Binary Generation Executable Binary 10,

The Open Problem Iterate until an optimal solution is found What about convergence? High-level Program Code Generation Tasks + Dependencies Suboptimal: Static Mapping/Scheduling ◦ Compute several solutions, Mapping WCRT with choose the best one Interferences Execution Order ◦ How many iterations? Release Dates Binary Generation Executable Binary Multi/Many-core processors are a game changer in the interaction between WCRT analysis and task mapping/scheduling 10,

Efficient Execution of Dependent Tasks on Many-Core Processors Hamza Rihani, Claire Maiza, Matthieu Moy Univ. Grenoble Alpes Verimag 11,

References I S. Altmeyer, R. I. Davis, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke. A generic and compositional framework for multicore response time analysis. In Proceedings of the 23rd International Conference on Real Time and Networks Systems , RTNS ’15, pages 129–138. ACM, 2015. J. Choi, D. Kang, and S. Ha. Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE) , pages 181–186. D. Dasari, V. Nelis, and B. Akesson. A framework for memory contention analysis in multi-core platforms. Real-Time Systems , pages 1–51, 2015. 12,

References II G. Giannopoulou, N. Stoimenov, P. Huang, and L. Thiele. Scheduling of mixed-criticality applications on resource-sharing multicore systems. In Embedded Software (EMSOFT), 2013 Proceedings of the International Conference on , pages 1–15, Sept 2013. A. Melani, M. Bertogna, V. Bonifaci, A. Marchetti-Spaccamela, and G. Buttazzo. Memory-processor co-scheduling in fixed priority systems. In 23rd ACM International Conference on Real-Time Networks and Systems (RTNS) , Lille, France, November, 2015. R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. Worst case delay analysis for memory interference in multicore systems. In Proceedings of the Conference on Design, Automation and Test in Europe , DATE ’10, pages 741–746. 13,

References III W. Puffitsch, E. Noulard, and C. Pagetti. Mapping a multi-rate synchronous language to a many-core processor. In Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th , pages 293–302. J. Walter and W. Nebel. Energy–aware mapping and scheduling of large–scale macro data–flow applications. In 1st International Workshop on Investigating Dataflow in Embedded Computing Architecture , 2015. 14,