Redundant Via Insertion Redundant Via Insertion with Wire Bending - - PowerPoint PPT Presentation

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Redundant Via Insertion Redundant Via Insertion with Wire Bending with Wire Bending

Kuang Kuang-

• Yao Lee,

Yao Lee, Shing Shing-

• Tung Lin and Ting

Tung Lin and Ting-

• Chi Wang

Chi Wang

Department of Computer Science Department of Computer Science National National Tsing Tsing Hua Hua University University Hsinchu Hsinchu, Taiwan , Taiwan

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Outline Outline

Preliminaries Preliminaries Problem definition Problem definition Minimum Minimum-

• weight maximum independent

weight maximum independent set formulation set formulation 0-

• 1 integer linear program based approach

1 integer linear program based approach Experimental results Experimental results Conclusion Conclusion

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Redundant via Redundant via

Enable a single via failure to be tolerated Enable a single via failure to be tolerated Improve the chip yield and reliability Improve the chip yield and reliability

N N S S E E W W

Single via Single via Redundant Via Redundant Via

Double Via

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Feasible double via Feasible double via

Feasible Infeasible

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v1

d1 d2

v1 v2

d3 d1 d2

v2

Wire bending Wire bending

Create more feasible double Create more feasible double vias vias Improve the insertion rate Improve the insertion rate

Insertion rate = 50% Insertion rate = 100%

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Wire bending (cont Wire bending (cont’ ’d) d)

The wires are allowed to be bent The wires are allowed to be bent A bending window of pre A bending window of pre-

• defined size is given

defined size is given

p p’ p’ p p p p’ p’

Bending window Bending window

Legal Illegal

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Double via insertion with wire bending Double via insertion with wire bending (DVI/WB) (DVI/WB)

Input Input

– – A routed design and a set of via A routed design and a set of via-

• related design rules

related design rules

Goal Goal

1.

• 1. To replace as many single

To replace as many single vias vias with double with double vias vias as as possible possible 2.

• 2. Minimize the

Minimize the wirelength wirelength increase due to wire increase due to wire bending bending

Constraints Constraints

– – Each single via either remains unchanged or is Each single via either remains unchanged or is replaced by a double via replaced by a double via – – After via replacement and wire bending, no design After via replacement and wire bending, no design rule is violated rule is violated

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Enhanced conflict graph Enhanced conflict graph

An undirected vertex An undirected vertex-

• weighted graph

weighted graph constructed from a detailed routing solution constructed from a detailed routing solution Vertex Vertex

– – a feasible double via a feasible double via

Edge Edge

– – cannot be inserted simultaneously cannot be inserted simultaneously

d3 d1 d2

d1 d2 d3

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Enhanced conflict graph Enhanced conflict graph

Each vertex is associated with a weight Each vertex is associated with a weight

– – The amount of The amount of wirelength wirelength increase caused by increase caused by inserting the corresponding double via inserting the corresponding double via

p’ p m2 m3 m4 p p’

Bending window

Weight = m1+m2+m3+m4

m1

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Theorem Theorem

The DVI/WB problem can be formulated The DVI/WB problem can be formulated as that of finding a minimum as that of finding a minimum-

• weight

weight maximum independent set ( maximum independent set (mWMIS mWMIS) from ) from the enhanced conflict graph the enhanced conflict graph

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Graph construction Graph construction

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N1 S1 E1 N2 S2 W2 E2 W3 S3 E3 W3

[Lee et al., ICCAD’06]

– Sweep-line-like approach – Cannot consider wire bending

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Graph construction Graph construction

1 2 3 4 4 1 3 2 5 5

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Graph construction Graph construction

6 6 K 1 2 3 4 5

K K

6 Bending window

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Graph construction Graph construction

1 2 3 4 5 5 6 8 7 6 K 7 8 4 1 3 2

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0-

• 1 ILP formulation

1 ILP formulation

} 1 , { ∈

i

R

∑ ∑

≤ ≤ ≤ ≤

− ⋅

8 1 8 1

|) SV | (

i i i i i

R W R C

Maximize

1 1

8 7 6 5 4 3 2 1

≤ + + + ≤ + + + R R R R R R R R 1 1

6 4 5 2

≤ + ≤ + R R R R

Subject to

1 2 3 4 5 6 K 7 8

Double-cut constraint

i

W max >

# of single vias Weight of vertex i Conflict constraint

External

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Speed Speed-

• up

up – – Pre Pre-

• selection

selection

Adapted from [Lee et al, ISPD Adapted from [Lee et al, ISPD’ ’08] 08]

– – No external edge No external edge – – Having the minimum weight among the Having the minimum weight among the vertices coming from the same single via vertices coming from the same single via

1 2 3 4 5 W2 W4 5 W5 6 8 7 6 W6 7 W7 8 W8 4 1 3 2

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Speed Speed-

• up

up – – Connected components Connected components

[Lee et al, ISPD [Lee et al, ISPD’ ’08] 08]

– – Divide into smaller 0 Divide into smaller 0-

• 1 ILP problems

1 ILP problems

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Overall approach Overall approach

• 1. Pre-selection
• 1. Pre
• 1. Pre-
• selection

selection

5 10 5 5 5 9 5

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Overall approach Overall approach

• 1. Pre-selection
• 1. Pre
• 1. Pre-
• selection

selection

5 5 5 9 5

2.Connected Components 2. 2.Connected Connected Components Components

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Overall approach Overall approach

• 1. Pre-selection
• 1. Pre
• 1. Pre-
• selection

selection

5 5 5 9 5

2.Connected Components 2. 2.Connected Connected Components Components

• 3. Solve 0-1 ILP

3.

• 3. Solve 0

Solve 0-

• 1 ILP

1 ILP

Maximize

∑ ∑

≤ ≤ ≤ ≤

− ⋅

5 1 5 1

2 10

i i i i i

R W R

Subject to

Λ

Maximize

∑ ∑

≤ ≤ ≤ ≤

− ⋅

4 1 4 1

2 6

i i i i i

R W R

Subject to

Λ

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Overall approach (cont Overall approach (cont’ ’d) d)

5 10 5 5 5 9 5

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Experiment Experiment setup setup

Linux based machine with 2.4GHz processor Linux based machine with 2.4GHz processor and 2GB memory and 2GB memory Adopted Adopted lp_solve lp_solve as our 0 as our 0-

• 1 ILP solver

1 ILP solver

5 5 357386 357386 99 99 44720 44720 C5 C5 5 5 151912 151912 415 415 17692 17692 C4 C4 5 5 127059 127059 85 85 18157 18157 C3 C3 5 5 41157 41157 211 211 5252 5252 C2 C2 5 5 24594 24594 20 20 4309 4309 C1 C1

#M #M-

• Layers

Layers # #Vias Vias #I/Os #I/Os #Nets #Nets Circuit Circuit

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Experimental results Experimental results – – Effectiveness of wire bending Effectiveness of wire bending

T(s T(s) ) |E| |E| |V| |V| #A #A-

• vias

vias T(s T(s) ) |E| |E| |V| |V| #A #A-

• vias

vias

1.36 1.36 2.09 2.09 1.33 1.33 1.06 1.06 1 1 1 1 1 1 1 1

Normalized Normalized

731 1025320 804268 296323 442 444754 574142 276032

C5 C5

184 371024 302904 119795 131 159691 220538 112076

C4 C4

157 357643 284072 104356 120 179307 215647 99142

C3 C3

41 114497 90541 33174 32 54376 67312 31464

C2 C2

27 64083 53504 20664 22 36714 43246 19796

C1 C1 with wire bending with wire bending w/o wire bending w/o wire bending Circuit Circuit

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Experimental results Experimental results – – # of inserted double # of inserted double vias vias

T(s T(s) ) #WB #WB #DVI #DVI T(s T(s) ) #DVI #DVI

1.18 1.18

• 1.06

1.06 1 1 1 1

Normalized Normalized

13.62 13.62 20256 20256 295383 295383 5.14 5.14 275437 275437 C5 C5 5.19 5.19 7798 7798 119256 119256 3.87 3.87 111657 111657 C4 C4 4.87 4.87 5146 5146 103934 103934 3.81 3.81 98888 98888 C3 C3 3.54 3.54 1720 1720 33101 33101 3.30 3.30 31411 31411 C2 C2 3.37 3.37 835 835 20567 20567 3.23 3.23 19754 19754 C1 C1

01ILP 01ILP– –DVI/WB DVI/WB 01ILP 01ILP– –DVI* DVI* Circuit Circuit

*[Lee et al., ISPD’08]

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Experimental results Experimental results – – Wirelength Wirelength increase increase

1.22 1.22

13.62 13.62 5.19 5.19 4.87 4.87 3.54 3.54 3.37 3.37 T(s T(s) )

1 1

9.02 9.02 4.41 4.41 4.42 4.42 3.43 3.43 3.30 3.30 T(s T(s) ) 01ILP 01ILP– –DVI/WB DVI/WB Rate(%) Rate(%) WL( WL(μ

μm

m) ) Rate(%) Rate(%) WL( WL(μ

μm

m) )

• 0.28

0.28

• 1

1

Normalized Normalized 0.10 0.10 2.57E+04 2.57E+04 0.36 0.36 9.27E+04 9.27E+04 C5 C5 0.10 0.10 9.79E+03 9.79E+03 0.32 0.32 3.11E+04 3.11E+04 C4 C4 0.10 0.10 6.30E+03 6.30E+03 0.39 0.39 2.47E+04 2.47E+04 C3 C3 0.10 0.10 2.12E+03 2.12E+03 0.39 0.39 8.21E+03 8.21E+03 C2 C2 0.10 0.10 9.96E+02 9.96E+02 0.32 0.32 3.22E+03 3.22E+03 C1 C1 ECG + 01ILP ECG + 01ILP– –DVI* DVI* Circuit Circuit

*[Lee et al., ISPD’08]

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Conclusions Conclusions

We studied the DVI/WB problem and We studied the DVI/WB problem and formulated it as a formulated it as a mWMIS mWMIS on the

• n the

enhanced conflict graph enhanced conflict graph We proposed an efficient 0 We proposed an efficient 0-

• 1 ILP based

1 ILP based approach to solve the approach to solve the mWMIS mWMIS problem problem The experimental results were shown to The experimental results were shown to support our approach support our approach

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Wire bending Wire bending

p p’ p’ p p p p’ p’

• Bending

window

• Bending

window

Legal Illegal