Via Pillar-aware Detailed Placement Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, and Shao-Yun Fang The Electronic Design Automation Laboratory Department of Electrical Engineering National Taiwan University of Science and Technology 1
Outline Introduction Algorithm Experiment Results Conclusion The EDA Lab, NTUSTEE 2
INTRODUCTION The EDA Lab, NTUSTEE 3
Detailed Placement In the VLSI physical design flow, placement consists of 3 stages: (1) Global placement (2) Legalization (3) Detailed placement Detailed placement focuses on improving the legalized placement solution, while keeping its legality Global Placement Legalization Detailed Placement Optimization • Wirelength • Density • Manufacturing rules • Lithography • Multi-row-height Cells • … The EDA Lab, NTUSTEE 4
Via Pillar Feature size has shrunk down to 7 nm and beyond The impact of wire resistance is significantly growing The circuit delay incurred by the metal wires is noticeable raising A new technique “ Via Pillar ” (or via pillar) is proposed 50% R delay vs. Total delay 40% 30% 20% 10% 0% 40nm 28nm 16nm 7nm 5nm The EDA Lab, NTUSTEE L. -C. Lu, Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend", ISPD, 2017 5
Structure of Via Pillar Structure of Via Pillar • Multiple vias • Multiple metal wires • Cross multiple layers (generally) Metal wire Pin of cell Via The EDA Lab, NTUSTEE 6
Benefits of Via Pillar Benefits of Via Pillar • Reduce Wire Resistance • Reduce Circuit Latency • Enhance Reliability • Enhance EM robustness Metal wire Pin of cell via The EDA Lab, NTUSTEE 7
Benefits of Via Pillar 50% R delay vs. Total delay 40% 30% 20% With Via Pillar 10% 0% 40nm 28nm 16nm 7nm 5nm L. -C. Lu, Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend", ISPD, 2017 The EDA Lab, NTUSTEE 8
Problem on Via Pillar Insertion Major issues that cause poor Insertion success rate: - Track Alignment Issue - Power/Ground Stripe Overlapping - Insufficient Margin Area The EDA Lab, NTUSTEE 9
Track Alignment Issue In our experiments, we found that the via pillar insertion may fail when the access point is not at a certain position w.r.t. its adjacent tracks M4 (success) M4 (failure) The EDA Lab, NTUSTEE 10
Track Alignment Issue (cont’d) In our experiments, we found that the via pillar insertion may fail when the access point is not at a certain position w.r.t. its adjacent tracks M5 (success) M5 (failure) The EDA Lab, NTUSTEE 11
Power/Ground Stripe Overlapping If the structure overlaps with a power/ground (PG) stripe, the insertion of the via pillar will fail Denser or wider PG strips will result in fewer eligible positions, more difficult to optimize the result VDD / VSS VDD / VSS VDD / VSS VDD / VSS VDD / VSS Via pillar-inserting cells Standard cells not concerning via-pillar The EDA Lab, NTUSTEE 12
Insufficient Margin Area If a via pillar structure overlaps with another via pillar or design boundaries, the insertion will fail Pin Via Pillar Via Pillar Design Boundary The EDA Lab, NTUSTEE 13
Previous Works The research on detailed placement have been developed in decade that address various issues Wirelength Density Manufacturing rules Lithography Multi-row-height Cells However, none of these works has focused on via pillar insertion in the detailed placement stage The EDA Lab, NTUSTEE 14
ALGORITHM The EDA Lab, NTUSTEE 15
Terminology An N-cell is a cell that is not concerning via pillar (normal cell) A V-cell is a cell that will be inserted a via pillar An eligible row/site/position indicates the position with maximized insertion rate No track alignment issue No overlap with any PG stripe MDC is the maximum displacement constraint that prevents from a large movement The EDA Lab, NTUSTEE 16
Algorithm Flow Input Eligible Positions Determination Global Move Legalization for V-cells Legalization for N-cells Output Check Legality Yes No Global Move for Congested Row Improvement The EDA Lab, NTUSTEE 17
Input • • Placement Result Configure file List of via-pillar inserting cells The EDA Lab, NTUSTEE 18
Eligible Positions Determination To enhance the via pillar insertability, we determine all the eligible positions for all V-cells 1. Filter out positions overlap with PG stripe 2. Filter out positions with track alignment issue Eligible Row Eligible Site Track 𝜀 𝜀 𝜀 Access point 𝜀 Track Track Track For each horizontal layers For each vertical layers The EDA Lab, NTUSTEE 19
Global Move The goal of this step is to move all V-cells in ineligible rows to eligible sites Find a best eligible position for a source V-cell The best eligible position is… ? An N-cell A V-cell or a white space Swap Move The EDA Lab, NTUSTEE 20
Global Move (cont’d) For each V-cell, We first find a best eligible position We traverse all eligible sites within 𝑁𝐸𝐷 and evaluate them by the cost function 𝑑𝑝𝑡𝑢 = 𝛽 ∙ ∆𝑋 + 𝛾 ∙ 𝐸 + 𝜍𝑄 𝐷 + 𝜏(1 − 𝑄 𝑇 ) 𝐷 = 𝐵𝑠𝑓𝑏(𝑂𝑑𝑓𝑚𝑚𝑡) 𝑄 𝐵𝑠𝑓𝑏(𝑆𝑝𝑥) ∙ ∆𝐵𝑠𝑓𝑏(𝑑𝑓𝑚𝑚) #𝑓𝑚𝑗𝑗𝑐𝑚𝑓 𝑡𝑗𝑢𝑓𝑡 𝑄 𝑇 = #𝑢𝑝𝑢𝑏𝑚 𝑡𝑗𝑢𝑓𝑡 𝑗𝑜 𝑠𝑝𝑥 ∆𝑋: Wirelength improvement or degradation 𝐸: Displacement 𝑄 𝐷 : Penalty of congested situation 𝑄 𝑇 : Penalty of density of eligible sites The EDA Lab, NTUSTEE 21
Global Move (cont’d) The overlaps among cells are permitted in this step To prevent from the sequence issue, we move a cell to a site if it is occupied by another V-cell Find a best eligible position for a source V-cell The best eligible position is… ? An N-cell A V-cell or a white space Swap Move There should be no V-cell in an ineligible row after this step The EDA Lab, NTUSTEE 22
DP-based Legalization Method (cont’d) Our legalizer is based on dynamic programming-based detailed placement algorithm [Taghavi et al., ICCAD, 2010] 𝐷 𝑗 𝐷 𝑗+1 𝐷 𝑗+2 𝐷 𝑗+𝑜 Cell … -M -M -M -M … -M+1 -M+1 -M+1 -M+1 … S -M+2 -M+2 -M+2 -M+2 T … … … … … M M M M Movement (-M~M) The EDA Lab, NTUSTEE 23
DP-based Legalization Method ( cont’d) However, the order of cells among V-cells and N-cells may have to be changed to obtain a result in better quality if the PG stripes are dense or the row is congested VDD / VSS VDD / VSS VDD / VSS VDD / VSS VDD / VSS N-cell V-cell The EDA Lab, NTUSTEE 24
DP- based Legalization Method (cont’d) Hence, we divide legalization procedure into two-stage to achieve the effect of re-ordering Legalization for V-cells Resolve overlaps among V-cells Ignore the existence of N-cells Legalization for N-cells Regard the V-cells as obstacles Achieve the effect of re-ordering among V-cells and N-cells The EDA Lab, NTUSTEE 25
Legalization for V-cell In the legalization of V-cells, we ignore the existence of N-cells and only legalize for V-cells 𝐷 𝑗 𝐷 𝑗+1 N-cell 𝑁 V-cell 𝐷 𝑗 𝐷 𝑗+1 Candidate sites for V-cell 𝐷 𝑗 𝐷 𝑗+1 The EDA Lab, NTUSTEE 26
Legalization for V- cell (cont’d) 𝑑𝑝𝑡𝑢 = 𝛽 ∙ ∆𝑋 + 𝛾 ∙ 𝐸 + 𝑄 M + 𝑄 E ∆𝑋: Wirelength improvement or degradation 𝐸: Displacement 𝑄 𝑁 : Penalty for violation of MDC 𝑄 𝐹 : Penalty of eligible site alignment 𝑄 𝑁 = ቊ 0, 𝑒𝑗𝑞𝑚𝑏𝑑𝑓𝑛𝑓𝑜𝑢 𝑥𝑗𝑢ℎ𝑗𝑜 𝑁𝐸𝐷 𝑄 𝐹 = ቊ0, 𝑗𝑔 𝑢ℎ𝑓 𝑡𝑗𝑢𝑓 𝑗𝑡 𝑓𝑚𝑗𝑗𝑐𝑚𝑓, ∞, 𝑒𝑗𝑡𝑞𝑚𝑏𝑑𝑛𝑓𝑜𝑢 𝑐𝑓𝑧𝑝𝑜𝑒 𝑁𝐸𝐷 ∞, 𝑝𝑢ℎ𝑓𝑠𝑥𝑗𝑡𝑓. The EDA Lab, NTUSTEE 27
Legalization for N-cell To achieve the effect of re-ordering among V-cells and N-cells, we regard the V-cells as obstacles without actually place it. 𝐷 𝑗 𝐷 𝑗+1 N-cell 𝑁 V-cell 𝐷 𝑗 𝐷 𝑗+1 Candidate sites for V-cell 𝑁 Obstacle 𝐷 𝑗 𝐷 𝑗+1 28 The EDA Lab, NTUSTEE
Legalization for N- cell (cont’d) 𝐷 𝑗 𝐷 𝑗+1 𝐷 𝑗 𝐷 𝑗+1 𝐷 𝑗+2 𝐷 𝑗+𝑜 Cell … -M -M -M -M … -M+1 -M+1 -M+1 -M+1 … S -M+2 -M+2 -M+2 -M+2 T … … … … … M M M M Movement (-M~M) The EDA Lab, NTUSTEE 29
Legalization for N- cell (cont’d) 𝐷 𝑗 𝐷 𝑗+1 𝐷 𝑗 𝐷 𝑗+1 𝐷 𝑗+2 𝐷 𝑗+𝑜 Cell … -M -M -M -M … -M+1 -M+1 … S -M+2 -M+2 -M+2 T … … … … … M M M M Movement (-M~M) The EDA Lab, NTUSTEE 30
Legalization for N- cell (cont’d) 𝑑𝑝𝑡𝑢 = 𝛽 ∙ ∆𝑋 + 𝛾 ∙ 𝐸 + 𝑄 M ∆𝑋: Wirelength improvement or degradation 𝐸: Displacement 𝑄 𝑁 : Penalty of MDC 𝑄 𝑁 = ቊ 0, 𝑒𝑗𝑞𝑚𝑏𝑑𝑓𝑛𝑓𝑜𝑢 𝑥𝑗𝑢ℎ𝑗𝑜 𝑁𝐸𝐷 ∞, 𝑒𝑗𝑡𝑞𝑚𝑏𝑑𝑛𝑓𝑜𝑢 𝑐𝑓𝑧𝑝𝑜𝑒 𝑁𝐸𝐷 The EDA Lab, NTUSTEE 31
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