Real Time Embedded Systems " Memories Memories " - - PowerPoint PPT Presentation

▶
real time embedded systems
SMART_READER_LITE
LIVE PREVIEW

Real Time Embedded Systems " Memories Memories " - - PowerPoint PPT Presentation

Apr 20, 2023 261 likes •1.14k views

Real Time Embedded Systems " Memories Memories " rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Charg de cours LSN/hepia Prof. HES 1998-2008 R.Beuchat / Memories 2 General classification of electronic memories Non-volatile

slide-1
SLIDE 1

1998-2008

R.Beuchat / Memories 2

rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Chargé de cours LSN/hepia

  • Prof. HES

Real Time Embedded Systems

" Memories Memories "

slide-2
SLIDE 2

1998-2008

3 R.Beuchat / Memories

General classification of electronic memories

  • Non-volatile Memories

ROM PROM EPROM EEPROM Flash EPROM

E lectrically E rasable P rogrammable R ead O nly M emory

  • Volatile Memories

Static RAM (RAM/SRAM)

S tatic S ynchronous

Dynamic RAM (DRAM/SDRAM, DDR)

D ynamic R andom A ccess M emory S ynchronous D ual D ata R ate

Z-RAM (Zero transistor)

NVRAM

NonVolatile RAM MRAM

Magnetoresistive RAM

FRAM Ferromagnetic RAM

slide-3
SLIDE 3

1998-2008

5 R.Beuchat / Memories

Objectives

  • Having an overview of the different kinds
  • f memories on the market
  • Understanding the internal architecture of

dynamic memories, specifically SDRAM

slide-4
SLIDE 4

1998-2008

6 R.Beuchat / Memories

Memory Model

Data: Content Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 . . . . . . . . 0 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0x00 0x01 0x7F

0 1 1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0

Random Access Memory : at Address DATA Write Read

slide-5
SLIDE 5

1998-2008

7 R.Beuchat / Memories

Content

  • Non Volatile Memories
  • Volatiles Memories : Static
  • Volatiles Memories : Dynamic

Asynchronous Synchronous Dual Data Rate RamBus Evolution / Market

slide-6
SLIDE 6

1998-2008

R.Beuchat / Memories 8

Non Volatile Memories

slide-7
SLIDE 7

1998-2008

R.Beuchat / Memories 57

Volatile Memories Dynamic Memories

slide-8
SLIDE 8

1998-2008

58 R.Beuchat / Memories

DRAM (asynchronous basic memory)

  • Main characteristics:

Dynamic Memory

Rom/Column Organization Control signals: /RAS, /CAS, /WR, (/OE)

Burst access possibilities:

Nibble mode Static Column Mode Page Mode Fast Page Mode (FPM) Extended Data Out (EDO)

slide-9
SLIDE 9

1998-2008

59 R.Beuchat / Memories

DRAM

Memorization elements All acceded on a row at the same time Power consummation

slide-10
SLIDE 10

1998-2008

60 R.Beuchat / Memories

DRAM

multiplexed Addresses: Row/Column

slide-11
SLIDE 11

1998-2008

61 R.Beuchat / Memories

DRAM

multiplexed Addresses: Row/Column

slide-12
SLIDE 12

1998-2008

62 R.Beuchat / Memories

DRAM

Data Bus : Separated In/Out Bi-directional

slide-13
SLIDE 13

1998-2008

63 R.Beuchat / Memories

DRAM

Processor interface : Address multiplexer Memories controller

slide-14
SLIDE 14

1998-2008

64 R.Beuchat / Memories

DRAM, circuits multiples

Control signals organization on a memory module Ex: 32 bits data bus width, with parity

slide-15
SLIDE 15

1998-2008

65 R.Beuchat / Memories

DRAM read access

slide-16
SLIDE 16

1998-2008

66 R.Beuchat / Memories

DRAM write access

slide-17
SLIDE 17

1998-2008

67 R.Beuchat / Memories

DRAM late write

slide-18
SLIDE 18

1998-2008

68 R.Beuchat / Memories

DRAM Read-Modify-Write

slide-19
SLIDE 19

1998-2008

69 R.Beuchat / Memories

DRAM Precharge time

  • Between 2 access there is the recovery

time

  • The vertical (column) lines are precharge

to an intermediate voltage

  • When access to the memory is done, the

driver is less stressed to transfer the high/low logical level

  • This take time !! ~30-50 ns
slide-20
SLIDE 20

1998-2008

70 R.Beuchat / Memories

DRAM Refresh

  • The memory need to be refreshed to

maintain its content

  • Particular Cycles :

RAS only CAS before RAS Hidden refresh

slide-21
SLIDE 21

1998-2008

71 R.Beuchat / Memories

DRAM Refresh

slide-22
SLIDE 22

1998-2008

72 R.Beuchat / Memories

DRAM Refresh

slide-23
SLIDE 23

1998-2008

73 R.Beuchat / Memories

DRAM Refresh

slide-24
SLIDE 24

1998-2008

74 R.Beuchat / Memories

DRAM Accès multiples, page

Page mode

slide-25
SLIDE 25

1998-2008

75 R.Beuchat / Memories

DRAM Accès multiples, nibble

Nibble mode

slide-26
SLIDE 26

1998-2008

76 R.Beuchat / Memories

DRAM Accès multiples, static column

Static column mode

slide-27
SLIDE 27

1998-2008

77 R.Beuchat / Memories

DRAM Accès multiples, static column

Static column mode

slide-28
SLIDE 28

1998-2008

78 R.Beuchat / Memories

DRAM Accès multiples, EDO

EDO

slide-29
SLIDE 29

1998-2008

79 R.Beuchat / Memories

  • Asynchronous Dynamic Memory
  • Added "Serial Register"
  • Transfer between Dynamic array and

serial line

  • Independent serial transfers

VRAM (Video RAM)

slide-30
SLIDE 30

1998-2008

80 R.Beuchat / Memories

Ex: First VRAM 64k x 4, 4 serial bits

VRAM (Video RAM)

slide-31
SLIDE 31

1998-2008

81 R.Beuchat / Memories

VRAM (Video RAM) simple model

slide-32
SLIDE 32

1998-2008

82 R.Beuchat / Memories

VRAM parallel register+counter+mux

slide-33
SLIDE 33

1998-2008

83 R.Beuchat / Memories

VRAM parallel register+counter+mux

  • The serial register is build from a parallel

register the full content of the selected line (Row) is transferred in a large register

  • During the column phase, the address is

transferred in a counter: the start address

  • f the line
  • The counter select a multiplexer, thus the

parallel register is transform in a serial register!

slide-34
SLIDE 34

1998-2008

R.Beuchat / Memories 84

SDRAM

Synchronous Dynamic RAM

slide-35
SLIDE 35

1998-2008

85 R.Beuchat / Memories

SDRAM (Synchronous DRAM)

  • synchronous DRAM Memories
  • 16 Mbits..256 Mbits
  • x4, x8, x16, x32
  • 3.3V, 2.5V 1.8V
  • Clk 200MHz
  • 2 Banks / 4 Banks
  • PC100 SDRAM standard
  • Command ACTIVE to send with the Row and Bank

address

  • Read, Write Command with Column address
  • Concurrent Precharge between 2 banks
slide-36
SLIDE 36

1998-2008

86 R.Beuchat / Memories

SDRAM

  • Clock to synchronized every signals
  • Internal Pipeline
  • New column address possible in every

transfer cycle

  • Internal banks available to shadow the

precharge

  • Self-refresh (Self-Refresh command )
slide-37
SLIDE 37

1998-2008

87 R.Beuchat / Memories

SDRAM

Bank0 Bank1

slide-38
SLIDE 38

1998-2008

88 R.Beuchat / Memories

SDRAM

slide-39
SLIDE 39

1998-2008

89 R.Beuchat / Memories

SDRAM

slide-40
SLIDE 40

1998-2008

90 R.Beuchat / Memories

SDRAM Cas Latency (CL) Read cycle

4 burst accesses

slide-41
SLIDE 41

1998-2008

91 R.Beuchat / Memories

SDRAM Write data with command

CL=3

slide-42
SLIDE 42

1998-2008

92 R.Beuchat / Memories

SDRAM

CL=2

slide-43
SLIDE 43

1998-2008

93 R.Beuchat / Memories

SDRAM 4 banks ex: IS42S32800B

  • Nb row (12) ≠

Nb Column(9)

  • 4 banks
  • x32 bits width (4x8bits)
  • 256 Mbits :

4 x 2M x 32

  • Masked by DQM<3..0>
slide-44
SLIDE 44

1998-2008

94 R.Beuchat / Memories

SDRAM 4 banks ex: IS42S32800B

See the full documentation

For all specific timings relationships

http://www.issi.com/pdf/42S32800B.pdf

slide-45
SLIDE 45

1998-2008

95 R.Beuchat / Memories

Module DIMM SDRAM

  • Module DIMM 100-Pin
  • Bus x32
  • Synchronous
  • SDRAM Memory
slide-46
SLIDE 46

1998-2008

96 R.Beuchat / Memories

SDRAM (x32, x36)

slide-47
SLIDE 47

1998-2008

97 R.Beuchat / Memories

SDRAM (x64, x72)

slide-48
SLIDE 48

1998-2008

98 R.Beuchat / Memories

PC100 SDRAM DIMM Dual In Line Memory module

  • Specification from Intel for DIMM 100MHz
  • EEPROM memory on the module for the

specification of the DIMM SPD : Serial Presence detect

  • Specification for memory from 64Mbytes to 1024

Mbytes (1GBytes)

  • Module without buffer
  • Module with register to be used with up to 36

chips

  • Old specification (historical)
slide-49
SLIDE 49

1998-2008

99 R.Beuchat / Memories

SGRAM Synchronous Graphic RAM

  • 128kx32, 256kx32, 512kx32
  • Synchronous
  • Double banque
  • Burst 1, 2, 4, 8 ou pleine page
  • Block Write, Write par bit
  • Auto precharge, auto refresh
  • 3.3V
slide-50
SLIDE 50

1998-2008

100 R.Beuchat / Memories

SGRAM Synchronous Graphic RAM

slide-51
SLIDE 51

1998-2008

101 R.Beuchat / Memories

SGRAM

slide-52
SLIDE 52

1998-2008

102 R.Beuchat / Memories

SGRAM

slide-53
SLIDE 53

1998-2008

103 R.Beuchat / Memories

Graphics Memory GDDR

  • Features

2.2V +/-0.1V VDD/VDDQ power supply supports 900 / 800MHz 2.0V VDD/ VDDQ wide range min/max power supply supports 700MHz 1.8V VDD/ VDDQ wide range min/max power supply supports 500 / 600MHz Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Calibrated output driver Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READ; with WDQScenter-aligned with data for WRITE Eight internal banks for concurrent operation Data mask (DM) for masking WRITE data

slide-54
SLIDE 54

1998-2008

104 R.Beuchat / Memories

Graphics Memory GDDR

  • Features

4n prefetch Programmable burst lengths: 4, 8 32ms, 8K-cycle auto refresh Auto precharge option Auto Refresh and Self Refresh Modes 1.8V Pseudo Open Drain I/O Concurrent Auto Precharge support tRAS lockout support, Active Termination support Programmable Write latency(1, 2, 3, 4, 5, 6) Boundary Scan Feature for connectivity test(refer to JEDEC std., not in this version of Specifications)

slide-55
SLIDE 55

1998-2008

105 R.Beuchat / Memories

Graphics Memory

slide-56
SLIDE 56

1998-2008

106 R.Beuchat / Memories

DDR Dual Data Rate

  • DDR-I

PC1600 = DDR 200MHz Data-rate (100 Clk x 2) 1.6Gb/Sec PC2100 = DDR 266MHz Data-rate (133 Clk x 2) 2.1Gb/Sec PC2400 = DDR 300MHz Date-rate (150 Clk x 2) 2.4Gb/Sec PC2700 = DDR 333MHz Data-rate (166 Clk x 2) 2.7Gb/Sec PC3000 = DDR 366MHz Data-rate (183 Clk x 2) 3.0Gb/Sec PC3200 = DDR 400MHz Data-rate (200 Clk x 2) 3.2Gb/Sec DDR-II PC4300 = DDR 533MHz Data-rate (266 Clk x 2) 4.3Gb/Sec

slide-57
SLIDE 57

1998-2008

107 R.Beuchat / Memories

Clock in Synchronous DRAM

  • SDRAM Clock:

rising edge only

  • DDR Clock:

both edge internal bus size = 2* external internal f = 1/2 *ext. f

  • DDR2 Clock:

both edge internal bus size = 4* external internal f = 1/4 *ext. f

slide-58
SLIDE 58

1998-2008

108 R.Beuchat / Memories

DDR Clock use

  • SDRAM / DDR are synchronous DRAM
  • SDRAM are working on rising-edge only
  • DDR are working on both edge of the clk

for the burst data transfer on the same row

  • f a bank
  • They are external clk and internal clk
  • Internal bus width can is growing with new

generation

slide-59
SLIDE 59

1998-2008

109 R.Beuchat / Memories

Clk SDRAM

http://www.elpida.com/pdfs/E0437E40.pdf

slide-60
SLIDE 60

1998-2008

110 R.Beuchat / Memories

Clk DDR

http://www.elpida.com/pdfs/E0437E40.pdf

slide-61
SLIDE 61

1998-2008

111 R.Beuchat / Memories

Clk DDR2

http://www.elpida.com/pdfs/E0437E40.pdf

slide-62
SLIDE 62

1998-2008

113 R.Beuchat / Memories

DDR Dual Data Rate

  • Synchronization for data transfers : DQs
  • Burst transfer on 2 edges of DQs
  • Synchronization with DQs :

DQs provided by the memory controller in write cycle DQs provided by the memory in read cycle DQs propagate in the same direction as data DDR : power supply 2.5V DDR-II : power supply 1.8V, ODT (On Die Termination) DDR-III : power supply 1.5V, ODT Data bus termination Vtt = Valim/2

slide-63
SLIDE 63

1998-2008

114 R.Beuchat / Memories

DDR Dual Data Rate

slide-64
SLIDE 64

1998-2008

115 R.Beuchat / Memories

DDR signaling

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf

slide-65
SLIDE 65

1998-2008

116 R.Beuchat / Memories

DDR signaling

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf

slide-66
SLIDE 66

1998-2008

117 R.Beuchat / Memories

DDR signaling

  • The SSTL_2 input receiver is typically a

differential pair common source amplifier. This receiver provides better gain and bandwidth, and the variation in threshold voltage is much tighter, since the threshold voltage

  • ffset is determined by identical size and

technology transistors in a differential pair configuration.

  • The result is that smaller input signal swings can

be used reliably.

  • Many variations and enhancements to this input

receiver topology are in use today.

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf

slide-67
SLIDE 67

1998-2008

118 R.Beuchat / Memories

DDR signaling

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf Double terminated output Single terminated output

slide-68
SLIDE 68

1998-2008

119 R.Beuchat / Memories

DDR signaling

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf VRef divider and filter

slide-69
SLIDE 69

1998-2008

120 R.Beuchat / Memories

VTT PCB

http://www.fairchildsemi.com/ms/MS/MS-6500.pdf

slide-70
SLIDE 70

1998-2008

121 R.Beuchat / Memories

VTT PCB

ML6554 Bus terminator Power http://www.fairchildsemi.com/ms/MS/MS-6500.pdf

slide-71
SLIDE 71

1998-2008

122 R.Beuchat / Memories

VTT PCB

ML6554 Bus terminator Power http://www.fairchildsemi.com/ms/MS/MS-6500.pdf 1A – 3A !! ~55°C

slide-72
SLIDE 72

1998-2008

123 R.Beuchat / Memories

DDR Dual Data Rate

slide-73
SLIDE 73

1998-2008

124 R.Beuchat / Memories

DDR/RamBus comparison

Memory name Type name Clock speed Voltage DDR clock speed Data Bus & Bandwidth

PC100 . 100MHz 3.3v . 64-bit, 0.8GB/s PC133 . 133MHz 3.3v . 64-bit, 1.05B/s PC1600 DDR200 100MHz 2.5v 200MHz 64-bit, 1.6GB/s PC2100 DDR266 133MHz 2.5v 266MHz 64-bit, 2.1GB/s PC2700 DDR333 166MHz 2.5v 333MHz 64-bit, 2.7GB/s PC3200 DDR400 200MHz 2.5v 400MHz 64-bit, 3.2GB/s PC4200 DDR533 266MHz 2.5v 533MHz 64-bit, 4.2GB/s

RDRAM PC800

400 400MHz . . 16-bit, 1.6GB/s

RDRAM PC1066

533 533MHz . . 16-bit, 2.1GB/s

RDRAM PC1200

600 600MHz . . 16-bit, 2.4GB/s

slide-74
SLIDE 74

1998-2008

125 R.Beuchat / Memories

SLDRAM (Synchronous Link DRAM )

  • SLD4M18DR400
  • 4Mx18 (75Mbits)
  • 400MHz rate
  • 800MB/s peak
  • 8 internal banks
  • Burst 4 or 8
  • Protocol paquet oriented
  • 2 data clock
  • 1 command clock
  • Programmable Delay

Read/Wite

  • 2.5V
  • Configuration Register
slide-75
SLIDE 75

1998-2008

126 R.Beuchat / Memories

SLDRAM

slide-76
SLIDE 76

1998-2008

128 R.Beuchat / Memories

RamBus RDRAM

slide-77
SLIDE 77

1998-2008

129 R.Beuchat / Memories

RamBus RDRAM

slide-78
SLIDE 78

1998-2008

130 R.Beuchat / Memories

RamBus RDRAM

slide-79
SLIDE 79

1998-2008

131 R.Beuchat / Memories

RamBus RDRAM

slide-80
SLIDE 80

1998-2008

132 R.Beuchat / Memories

RamBus RDRAM

slide-81
SLIDE 81

1998-2008

138 R.Beuchat / Memories

RamBus RDRAM

slide-82
SLIDE 82

1998-2008

139 R.Beuchat / Memories

RamBus RDRAM

slide-83
SLIDE 83

1998-2008

140 R.Beuchat / Memories

RamBus RDRAM

slide-84
SLIDE 84

1998-2008

141 R.Beuchat / Memories

RamBus RDRAM

slide-85
SLIDE 85

1998-2008

143 R.Beuchat / Memories

RamBus RDRAM

slide-86
SLIDE 86

1998-2008

144 R.Beuchat / Memories

RamBus RDRAM