PXD9 Technology & Design Status Rainer Richter MPI - - PowerPoint PPT Presentation

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PXD9 Technology & Design Status Rainer Richter MPI Semiconductor Lab 12 International Workshop on DEPFET Detectors and Applications, R. H. Richter, HLL Wetzlar, 5. February 2013 Outline - Production status - Technology change to

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SLIDE 1

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

PXD9 Technology & Design Status

Rainer Richter MPI Semiconductor Lab

  • R. H. Richter, HLL
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SLIDE 2

Outline

  • Production status
  • Technology change to overcome the odd/even pedestal

shift problem after radiation

  • Design modifications to improve yield and testability
  • Update of 3d simulations

final doping profils expected operation windows (voltage) ?

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 3

Process sequence – after SOI

  • Oxidation
  • Transfer of alignment marks from BOX->backside->frontside
  • Global n-implantation (nd0n)
  • Nitride deposition
  • 1. Poly deposition, implantation, recrystalization (Sept. 2012)
  • 1. Poly lithography and etching
  • 1. Poly oxidation
  • Nitride etching
  • Litho and implantation – pshn (threshold adjustment )
  • Litho and implantation – pdpn (pot. barrier beneath Clear)
  • Litho and implantation – nd1n (internal Gate)
  • Litho and implantation – noxn (Clear)
  • 2. Poly deposition, implantation, recrystalization
  • 2. Poly lithography and etching
  • 2. Poly oxidation
  • Litho and implantation – pson (Source)

PXD9 Technology Status (i)

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 4

Production Status

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 5
  • Litho and implantation – pson (Source)
  • 2. Poly oxidation
  • Litho and implantation – poxn (Drain and Drift)
  • Nitride, Oxide deposition
  • Contacts co1n (part 1)
  • co1n (part 2)
  • Al1n sputter and litho - by end of March - Module design has to be defined !
  • first electrical tests
  • ZMI deposition
  • Contacts co2n
  • al2n sputter and litho
  • electrical tests

Back thinning, BCB, Cu, Passivation …

PXD9 Technology Status (ii)

Next steps

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 6

PXD9 – Technology Status (iii)

  • riginally planned to be

defined by 1 mask (poxn) as in PXD6 After poly oxidation !

Source, Drain, Drift Implantation

DRIFT DRIFT CG C G D S D

HE n HE p

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 7

H.4.1.09

7

The odd even pedestal problem

Results from Bonn

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 8

H.4.1.09

8

After electron irradiation

  • f 15 kGy

Initial state

Results from Bonn

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 9

H.4.1.09

9

After electron irradiation

  • f 15 kGy

Odd rows Even rows

Results from Bonn

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 10

Where does it come from?

implanted after oxidation poly oxide acts as lateral spacer DRIFT DRIFT CG C G D S D

HE n HE p

Bad connection between Source and channel Small region where connection is given by threshold adjust implant only (much lower boron concentration) Slight shadow effects during etching and implantation can cause asymmetries

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 11

Bad Source – Channel Connection 1018 1017 VG = -3V, VD= -3V 2D Simulation Hole concentration along the channel

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 12

What can we do? Implant before oxidation 1018 1017 1018 1017 VG = -3V, VD= -3V Id = 103 µA Id = 113 µA after Ox. before Ox. 1018 1017 Id = 114,5 µA before oxidation + optimized implantation parameter

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 13

Implications (i) Need of two implantations instead of one

Preserving the nice low field conditions at drain

CG C G D S D DRIFT

HE n HE p

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 14

Implications (ii)

Yield lesson from PXD6: Relaxing the topology Clear line must run parallel to Source

  • > asymmetric Source contact

Sheet resistance 300Ohm/sq. (3x lower than in the old technology due

to better implant activation)

Estimation: @Id=80µA, gm=50µS

  • > I ≈ 4µA

We will see an odd-even behavior but no change with radiation

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 15

Fault tolerant design Shorts between neighoring Drain lines (2nd metal when climbing over 1st metal (severe problem if S/D short) improve technology, relax topology, testing features

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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Design for testability Matrix Cutting edge ‘removable‘ test pad array 16 x 64

Aim: test all drain lines after 2nd metal with a probe card or ‘flying needle‘ (repair if necessary by overetching, or repeating the litho), A significant number of Depfet IV ca be taken. Sacrifice test matrices and structures to provide the space 4.5mm

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 17

Removing of the metal 2 connections after the tests Matrix Cutting edge ‘removable‘ test pad array 16 x 64 coarse mask to disconnect the test pads by etching the 2nd metal traces

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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Drain Fanout to DCD (i) Former design contains interleaved metal 1 und metal 2 lines Poly guard ring structure of punch through contact (-80V) Dangerous due to the weaker insulator (poly/first metal) 500nm oxide

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 19

Drain Fanout to DCD (ii) All lines are routed now in metal2

  • > oxide thickness 1.5µm
  • > smoother edge coverage

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 20

Drain Fanout to DCD (iii)

  • > smaller lines, partially compensated by use of larger

fanout angles than 45 smallest line width: 6.7µm (in matrix 7µm)

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 21

PXD9 - Operation Windows (voltages) VD=-3V, Vdrift=-5V, Vcg=-0.5V, Vc=3V, Vb=-28V All 3d simulations with revised implantation parameters (applied to PXD9), also with ‘New Source Technology‘

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 22

PXD9 - Operation Windows (voltages) VG=3V, VD=-3V, Vdrift=-5V, Vcg=-0.5V, Vc=3V, Vb=-28V

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 23

PXD9 - Operation Windows (voltages) VG=6V, VD=-3V, Vdrift=-5V, Vcg=-0.5V, Vc=3V, Vb=-28V

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 24

Charge collection (10.000 e/h pairs generated at backplane) Vclg = +4V

  • K. Gärtner

WIAS Berlin

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 25

ClearGate Voltage Range ‘irradiated‘ simulated by Vclg=5V corresponds to Nox ≈ 1012cm-2 Non irradiated Vclg=-0.5V Result of the new PXD9-Clear-Technology (As dop) Limitation is not given anymore by weak Clear barriers (back inj.) But by electron overflow from internal gate to clear gate

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 26

Confirmed by Trajectories

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 27

Next steps: Gated Mode + Cap. Coupled Clear Gate Simulations with ‘buildt in‘ coupling factor between Clear and ClearGate (30%) First results – junk charge suppression Vclear =15V  Vclear =11V 

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 28

Operation at Vd = -3V, instead of -5V Advantages less power (60%) less rad. damage in CG Oxide lower electric fields at Drain regions (gated mode) (less noisy pixel) less gm (more rad. tolerant) Drawbacks less gq ( about 10% for thin oxides - simulations ) slightly worse ‘Blind selectivity‘ (Gated mode) Need for experimental verification ! (laser, source, TB)

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 29

Summary and Schedule issues

  • PXD9 matrix design is finished , more failure tolerance and features for

testability are included

  • Module design (balcony and EOS)

work is ongoing (Christian Kreidl) waiting for input (system simulations and EMCM results)

  • > Module Session

deadline: April 2013 ?

  • First PXD9 second polysilicon finished, all but one implantations done

processing: faster than planned (automatic inspection,

  • wn implantation facility … )
  • Technological solution for the odd-even problem (radiated sensors)
  • Start of the second PXD9 batch had to be delayed, SOI material is available

technician quit, we hired new personal (needs training)

  • 3D studies on operation windows: Vback, Vclg

We expect safer operation as with PXD6 matrices

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL
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SLIDE 30

Next steps: Gated Mode + Cap. Coupled Clear Gate

  • Cap. Coupling between Clear and ClearGate makes Clear much easier

(lower Clear_hi voltages) In the chosen design we get it for free: almost 30% coupling between ClearGate and Clear But we can not switch off the coupling it‘s ‘buildt in‘ Unfortunately we can test this just on very big matrices (not yet done) So we have to rely on simulations

12 International Workshop on DEPFET Detectors and Applications, Wetzlar, 5. February 2013

  • R. H. Richter, HLL