OpenMPL : An Open Source Layout Decomposer Wei Li 1 , Yuzhe Ma 1 , - - PowerPoint PPT Presentation

OpenMPL: An Open Source Layout Decomposer

Wei Li1, Yuzhe Ma1, Qi Sun1, Yibo Lin2, Iris Hui-Ru Jiang3, Bei Yu1, David Z. Pan4

1The Chinese University of Hong Kong, 2Peking University, 3National Taiwan University, 4University of Texas at Austin

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1940 1950 1960 1970 1980 1990 2000 2010 2020 10,000,000,000 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 Intel Microprocessors

Invention of the Transistor

10 1 0.1 0.01

45nm

Year Number of Transistors per Integrated Circuit

Moore’s Law

Process Technology (µm

)

4004 8086 286 386 486 Pentium Pentium II Pentium 4 Core 2 Duo Core i7

Doubles every 2.1 yrs 2 / 21

AI / Cu / W wires Planar CMOS LE Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires Planar CMOS LE 10 nm 7 nm 5 nm 3 nm FinFET LELE W LI Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires Planar CMOS LE HNW VNW eNVM LELELE SADP SAQP

EUV LELE

10 nm 7 nm 5 nm 3 nm EUV EUV EBL

EUV DSA

Cu Doping 3D IC

Opto Connect Graphene CNT

FinFET LELE W LI Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires Planar CMOS LE HNW VNW eNVM 10 nm 7 nm 5 nm 3 nm Cu Doping 3D IC

Opto Connect Graphene CNT

FinFET W LI EUV EUV EBL

EUV DSA

LELE LELELE SADP SAQP

EUV LELE

Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

Multiple Patterning Litho (MPL)

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Multiple Patterning Layout Decomposition

a b

a b c d

(a) Original layout

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Multiple Patterning Layout Decomposition

a b

a b c d

(a) Original layout

a b

a b c d

(b) TPL layout with conflicts

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Multiple Patterning Layout Decomposition

a b

a b c d

(a) Original layout

a b

a d2 b c1 d1 c2

(b) Layout graph

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Multiple Patterning Layout Decomposition

a b

a b c d

(a) Original layout

a b

a d2 b c1 d1 c2

(b) Layout graph

a b

a d2 b c1 d1 c2

(c) Coloring on layout graph

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Multiple Patterning Layout Decomposition

a b

a b c d

(a) Original layout

a b

a d2 b c1 d1 c2

(b) Layout graph

a b

a d2 b c1 d1 c2

(c) Coloring on layout graph

a b d c2 c1

(d) Final decomposed layout

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Mathematical Formulation

◮ Some conflicts can be solved by Stitch Insertion.

f b a c d2 d1 e2 e1

k Pattern Layout Decomposition

min

x

• eij∈CE

cij + α ×

• eij∈SE

sij, s.t. cij = {xi == xj}, ∀eij ∈ CE, sij = {xi = xj}, ∀eij ∈ SE, xi ∈ {0, 1, ..., k}, ∀i ∈ V. ◮ xi is a variable for the k available colors of the pattern vi. ◮ cij is a binary variable representing conflict edge eij ∈ CE. ◮ sij stands for stitch edge eij ∈ SE.

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Research Trend for Layout Decomposition

An UNDERESTIMATION from Google Scholar

4 7 5 10 12 11 12 9 2 1 2 4 6 8 10 12 14 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

# of Researches Papers

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Challenges in Layout Decomposition Research

Complicated workflow and huge development overhead ◮ GDSII parsing and writing ◮ Layout graph construction and stitch insertion ◮ Graph simplification and core solvers

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Challenges in Layout Decomposition Research

Complicated workflow and huge development overhead ◮ GDSII parsing and writing ◮ Layout graph construction and stitch insertion ◮ Graph simplification and core solvers Lack of reusable code and repeatability ◮ Need to develop from scratch ◮ Only share executable binaries instead of source code

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Challenges in Layout Decomposition Research

Complicated workflow and huge development overhead ◮ GDSII parsing and writing ◮ Layout graph construction and stitch insertion ◮ Graph simplification and core solvers Lack of reusable code and repeatability ◮ Need to develop from scratch ◮ Only share executable binaries instead of source code No consistent framework for fair comparison ◮ Different implementations to the same algorithm ◮ Hard to make detailed comparison in depth

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OpenMPL 2.0: Open-Source Layout Decomposition Tool

https://github.com/limbo018/OpenMPL

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Workflow

Layout Graph Construction

Independent Component Computation

Input Layout Stitch Candidate Generation Decomposition Solver Graph Simplification Simplified Graph Recovery Output Masks

Merge 4-Cliques Hide Small Degree Biconnected Component Decomposition SDP ILP Backtracking Dancing Links

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Design Principles

◮ Decoupled design stages ◮ Graphs for communications among

kernel stages

◮ Efficiency and generality for different

mask data

Layout Graph Construction Independent Component Computation Input Layout Stitch Candidate Generation Decomposition Solver Graph Simplification Simplified Graph Recovery Output Masks Merge 4-Cliques Hide Small Degree Biconnected Component Decomposition SDP ILP Backtracking Dancing Links 9 / 21

Extensible API to Incorporate New Algorithms

◮ Create a solver

// A solver class class InstantColoring : public Coloring { public: // g is a boost::graph InstantColoring(g); protected: virtual double coloring() { // override base function // return cost } };

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Extensible API to Incorporate New Algorithms

◮ Create a solver

// A solver class class InstantColoring : public Coloring { public: // g is a boost::graph InstantColoring(g); protected: virtual double coloring() { // override base function // return cost } };

◮ Integrate the solver

// define a solver switch (algorithm) { case BruteForce: solver = new BruteForce (g); case InstantColoring: solver = new InstantColoring (g); ... } ... // solve coloring (*solver)();

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OpenMPL 2.0: Open-Source Layout Decomposition Tool

We implement several layout decomposition solvers. ◮ Backtracking: Use DFS algorithm to find the solutions [Yu+,ICCAD’13].

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OpenMPL 2.0: Open-Source Layout Decomposition Tool

We implement several layout decomposition solvers. ◮ Backtracking: Use DFS algorithm to find the solutions [Yu+,ICCAD’13]. ◮ Integer Linear Programming: Convert the problem into linear programming by binary

encoding of vertex colors [Yu+,ICCAD’11].

◮ Dancing Links: Treat the problem as an exact cover problem and solve it in the BFS

style [Chang+,DAC’16].

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OpenMPL 2.0: Open-Source Layout Decomposition Tool

We implement several layout decomposition solvers. ◮ Backtracking: Use DFS algorithm to find the solutions [Yu+,ICCAD’13]. ◮ Integer Linear Programming: Convert the problem into linear programming by binary

encoding of vertex colors [Yu+,ICCAD’11].

◮ Dancing Links: Treat the problem as an exact cover problem and solve it in the BFS

style [Chang+,DAC’16].

◮ Semidefinite Programming: Use SDP to relax the problem and solve it in polynomial

time [Yu+,ICCAD’11].

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Layout Simplification

Reduce the graph size and therefore reduce the computation complexity. ◮ Level 0: No Simplification. Do not conduct any simplification. ◮ Level 1: Hide small degree. Temporarily remove nodes with low degree

[Yu+,TCAD’15] [Lin+,SPIE’16].

◮ Level 2: Merge 4-Clique. Detect and merge sub-4-clique structures [Lin+,SPIE’16]. ◮ Level 3: Biconnected component decomposition. Partition original graph into

independent components [Kahng+,ICCAD’08].

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Additional Features

◮ Multithreading: Solve components in

parallel.

◮ Stitch Insertion: Insert stitches to solve

some conflicts.

◮ Shape Friendly: Specify the shape

(POLYGON or RECTANGLE) easily.

a e d f c b b c a

b’

d f e 2 1

a b

a d2 b c1 d1 c2

a b c d e P 13 / 21

Command Line Options

Selected Options Descriptions

• coloring_distance

a floating point number indicating number of coloring distance in nanometer

• color_num

an integer indicating number of masks (colors) < 3|4 >

• simplify_level

an integer indicating graph simplification level < 0|1|2|3 >

• path_layer

an integer indicating layer for conflict edges

• precolor_layer

an integer indicating layer for pre-colored patterns

• uncolor_layer

an integer indicating layer for coloring

• algo

algorithm type < ILP|BACKTRACK|LP|SDP >

• shape

shape mode < RECTANGLE|POLYGON >

• use_stitch

use stitch to avoid conflict

• gen_stitch

generate stitch candidate

• weight_stitch

weight of stitch

• thread_num

an integer indicating maximum thread number

• verbose

toggle controlling screen messages

• dbg_comp_id

debug component id

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Experimental Settings

◮ Triple Patterning Lithography ◮ Conducted on modified ISCAS benchmarks from [Yu+,ICCAD’13] ◮ Coloring distance: 120nm for the first ten cases and 100nm for the last five cases.

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Experimental Results

(a) total_c1, TPLD, SDP coloring process. (b) total_c2, TPLD, SDP coloring process.

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Experimental Results – Quality

25 50 75 100 # conflicts Backtracking ILP SDP Dancing Links C 4 3 2 C 4 9 9 C 8 8 C 1 3 5 5 C 1 9 8 C 2 6 7 C 3 5 4 C 5 3 1 5 C 6 2 8 8 C 7 5 5 2 S 1 4 8 8 S 3 8 4 1 7 S 3 5 9 3 2 S 3 8 5 8 4 S 1 5 8 5 50 100 150 200 250 # stitches

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Experimental Results – Runtime

C 4 3 2 C 4 9 9 C 8 8 C 1 3 5 5 C 1 9 8 C 2 6 7 C 3 5 4 C 5 3 1 5 C 6 2 8 8 C 7 5 5 2 S 1 4 8 8 S 3 8 4 1 7 S 3 5 9 3 2 S 3 8 5 8 4 S 1 5 8 5 10

3

10

2

10

1

100 101 102 Runtime (s) Backtracking ILP SDP Dancing Links

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Quality and Runtime Tradeoffs

Backtracking ILP SDP Dancing Links Quality Efficiency

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Conclusion

Open-source layout decomposition framework ◮ Four layout decomposition solvers; ◮ Four graph simplification strategies; ◮ Multithreads, stitch insertion supported and shape frinedly.

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Conclusion

Open-source layout decomposition framework ◮ Four layout decomposition solvers; ◮ Four graph simplification strategies; ◮ Multithreads, stitch insertion supported and shape frinedly. Future Work ◮ Efficiency: hardware acceleration. ◮ Quality: post refinement.

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Thank You

Wei Li (wli@cse.cuhk.edu.hk) Yuzhe Ma (yzma@cse.cuhk.edu.hk) Qi Sun (qsun@cse.cuhk.edu.hk) Yibo Lin (yibolin@pku.edu.cn) Iris Hui-Ru Jiang (huiru.jiang@gmail.com) Bei Yu (byu@cse.cuhk.edu.hk) David Z. Pan (dpan@ece.utexas.edu)

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