TEG: A New Post-Layout TEG: A New Post-Layout Optimization Method - - PDF document

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April 8, ISPD’02

TEG: A New Post-Layout Optimization Method TEG: A New Post-Layout Optimization Method

Shuo Zhang Wayne Dai

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Design optimization in post-layout stage TEG: A new post-layout optimization method Topological layout and operations in TEG Experimental results Conclusion

Outline Outline

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Physical Design Flow Physical Design Flow

Floorplanning Global Routing Detail Routing Placement IO Pad Placement Power/Ground Routing Clock Tree Synthesis

Post Post-

• layout:

layout: after detail routing, after detail routing, precise wire geometry precise wire geometry information is available. information is available.

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PD:Verification vs. Modification PD:Verification vs. Modification

estimated estimated Design Design Verification Verification accurate accurate Design Design Modification Modification easy easy difficult difficult

Power/Ground Routing Global Routing Floorplanning Detail Routing Placement IO Pad Placement Clock Tree Synthesis Extraction and Verification Design Optimization

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Post-layout Optimization Post-layout Optimization

Whether the design can be verified and analyzed precisely? What and where is the design problem? What layout optimization or modification should be performed? How modifications can be achieved with geometry constraints all over the layout?

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TEG: A Post-layout Optimization Method TEG: A Post-layout Optimization Method

Post-layout Optimization Detail Routing Extraction & Verification

Geometry Layout

layout problems

Topological Layout

TEG TEG

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Layout: Geometry vs. Topological Layout: Geometry vs. Topological

• Each net has determined

geometry path.

• Net path: a sequence of hard

wire segments.

• Any layout change is restrained

by surrounding wire segments.

• Each net has wiring topology.
• Wiring topology: relationships

between wires and layout features.

• No geometry wire, no wire

constraints. Topological Geometry

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Topological Layout Optimization Flow Topological Layout Optimization Flow

Post-layout Optimization Detail Routing Extraction & Verification

Geometry Layout

layout problems

Topological Layout

Topological DRC DRV Solver Layout Modification geometry transform topology extraction layout

• perations

remove DRVS DRVS

TEG TEG

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Topological Layout Encoding Topological Layout Encoding

Geometry

• Rubber Band Sketch: represents wires as rubber-bands.

+ Clear and straightforward layout change operation.

– Data size grows dramatically as design size increases.

RBS

1 1 3 1 4 4 2

Yu’s Yu’s encoding (1997): represents wire paths as the numbers of crossing wires on each triangulation edge. + Data size is significantly decreased.

– Many computations are required. – Only support uniform design rule.

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TEG: Improved from Yu’s, representing wires as crossing points between wire path and edges in the layout triangulation.

+ Capability: Designed for the large scale applications A small design (3k nets/8.6k pins) RBS:TEG:Yu = 2.7:1.1:1.0 Large scale designs TEG/Yu = 105% ~ 114% + Practicability: Support multiple spacing/width, practical design rules + Efficiency: Good support for topological layout operations Design rule check, DRV solver, layout change, topology extraction

Geometry TEG

TEG: Triangulation Encoding Graph TEG: Triangulation Encoding Graph

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Topological Design Rule Check Topological Design Rule Check

DRC: Whether a topological layout represents a valid geometry layout without any design rule violations (ROUTABILITY). Classic Routability Theorem (Maly 1990): A layout is routable if and only if all cuts are safe. O(n2) cuts, n – number of features

fa fb

w1 w2 w3

Sa1 S12 S23 S3b

flow capacity

A cut is safe: flow <= capacity, otherwise it is a DRV

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semi-open area op

TEG: Sealing Pair Routability Theorem TEG: Sealing Pair Routability Theorem

A layout is routable if all SPs are sealed in TEG. O(n) SPs

To determine the status of one SP, it is a recursive process with

constant time in each recursive-call.

Experimental results show there are totally O(n) recursive-calls.

s v1 v2 e Sealing pair (s, e) SP: a vertex-edge pair of a triangle in the layout triangulation. SP Status: unsealed -- a DRV is found in the determining process sealed -- each cut between s and any vertex inside op is safe if there is no DRV between inside op. (v1, sv2), (v2, sv1)

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Geometry TEG

• A DRV: not enough

layout resource in the local area, defined by surrounding features (terminals, vias…).

TEG: Design Rule Violation Solver TEG: Design Rule Violation Solver

DRV Solver: Move resource to the violation area; move DRV toward the resource area. DRV solvers gives each layout change as much resource as possible from the global view of the layout.

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TEG: Layout Modification TEG: Layout Modification

Core change operation in TEG: Vertex-moving

Key element in DRV solver Via relocation, obstacle/cell moving, buffer insertion…

Vertex-moving algorithm

Triangulation reconstruction and encoding update Running time: O(m·n), n – number of wires,

m – number of vertices influenced by moving.

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Examples: Cells (4.9K∼134K), Nets (5.0K∼41.8K), Pins (26K∼330K)

50 100 150 200 250 300 350 D1 D2 D3 D4 D5 D6

#Cells (K) #Nets (K) #Pins (K) TEG (MB)

Experimental Results Experimental Results

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1. Import the original routed design (LEF/DEF) into TEG. 2. Modification: 500 randomly selected via-moving 3. Topological DRC then DRV solver 4. Geometry Transform. PIII 550, 768MB memory, Linux platform

Running Time - Setup Running Time - Setup

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50 100 150 200 250 300 350 400 450 500

D1 D2 D3 D4 D5 D6

seconds

Import Mod. DRC Solver G-Trans

Running Time Running Time

Mod: 5000 via-moving, DRC: ~30000 SPs, Solver: 10 DRVs

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Layout D1 (~5%) in Cadence SE Layout D1 (~5%) in Cadence SE

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Layout D1 (~5%) in TEG Layout D1 (~5%) in TEG

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Original Layout Original Layout After wire sizing After wire sizing

Fix crosstalk-delay, reduce IR-drop …

Wire Sizing by TEG Wire Sizing by TEG

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Reduce wire density difference: decrease CMP process variation, improve yield and manufacturability…

Original Layout Original Layout After wire distribution After wire distribution

Wire Distribution by TEG Wire Distribution by TEG

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In post-layout stage, the challenge is how to achieve preferred layout modifications: even the small change is not acceptable due to the limited local resource. TEG: A new post-layout optimization method which processes the layout topologically, with an improved topological layout encoding mode and a set of layout

• peration procedures.

TEG provides an incremental layout modification environment for post-layout optimizations. TEG is efficient and effective for industry IC designs.

Conclusion Conclusion