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Prototyping to Design: Early Analysis for Power Distribution - - PowerPoint PPT Presentation

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ISPD 2009 Prototyping to Design: Early Analysis for Power Distribution Network Kai Wang, Aveek Sarkar, Norman Chang, Shen Lin 2009-4-12 Apache Design Solutions Inc. Outline Power integrity challenges Early analysis overview Power

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SLIDE 1

Prototyping to Design:

Early Analysis for Power Distribution Network

Kai Wang, Aveek Sarkar, Norman Chang, Shen Lin Apache Design Solutions Inc. 2009-4-12

ISPD 2009

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SLIDE 2

Outline

Power integrity challenges Early analysis overview Power distribution Power grid planning Static analysis Dynamic analysis Power switch optimization Early CPM

2009-4-12 ISPD 2009

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SLIDE 3

Whatever the chip does

2009-4-12 ISPD 2009

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SLIDE 4

It is all about Switching Current

2009-4-12 ISPD 2009

gnd vdd

C_load

Worst drop! Worst drop!

time

average

Current Consumption Case A: Load C & Freq f Case A: Load C & Freq f Case B: Load 2C & Freq Case B: Load 2C & Freq ½ ½f f

Same Average Same Average but Different Dynamic Drop! but Different Dynamic Drop!

Switching Power: Switching Power:

Average current = f(freq, charge, V) = ½ C.V2.freq Peak current = f(slew, charge, transition, V)

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SLIDE 5

Voltage Drop Impacts

2009-4-12 ISPD 2009

Δ ΔVmin Vmin ok?

  • k?

V time

FF 1 clk

? ?

vdd gnd

Logic Failure? Logic Failure?

Signal time

t1

Ideal True

Δ Δt t

Δ ΔV@t1 ok? V@t1 ok?

V time

t1

Timing Failure? Timing Failure?

V time

Resonance freq Resonance freq

Clock time

jitter jitter

Clock Failure? Clock Failure?

Ideal

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SLIDE 6

Noise Integrity Challenges

2009-4-12 ISPD 2009

Voltage Drop Voltage Drop Voltage Drop Functional and timing malfunction Functional and timing malfunction Timing/Jitter Timing/Jitter Timing/Jitter Package-induced timing uncertainty Package-induced timing uncertainty ESD ESD ESD Low yield from electrostatic discharge Low yield from electrostatic discharge Substrate Substrate Substrate Analog failure from digital noise injection / coupling Analog failure from digital noise injection / coupling EMI EMI EMI Excessive chip emission and high electromagnetic interfere Excessive chip emission and high electromagnetic interfere Package Package Package Inadequate package selection for noise and heat toleration Inadequate package selection for noise and heat toleration

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SLIDE 7

Why Early Analysis?

Time-to-Result breakdown for power sign-off

flow

Time to collect clean data ~40% Time to setup the flow/tool ~30% Time to run the analysis ~10% Time to interpret results ~20%

How to improve?

Optimize project setup Trained users Start sooner!

2009-4-12 ISPD 2009

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SLIDE 8

Why Early Analysis?

2009-4-12 ISPD 2009

Tape Out P&R Front End Fast Iteration No Iteration

Prototyping Prototyping Prototyping Optimization Optimization Optimization SignOff SignOff SignOff Failure Failure Failure Cost of Cost of Failure Failure

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SLIDE 9

SoC Power Flow

2009-4-12 ISPD 2009

RTL / Block Power Estimation Partition / Floorplan Initial Cell Placement Trial Routing Detailed Placement & Routing Manufacturing

Block-level & Full-chip Design Analysis

Full-chip transient Vectorless and VCD dynamic On-chip inductance

Early Stage Design & Analysis

Grid / pad / switch prototyping Chip power model Package selection Clamp cell placement guidance

Pre/Post Silicon Diagnosis

Root cause identification Chip power model

Full-chip Signoff (Pass/Fail)

IR / DvD Jitter Thermal EM Timing

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SLIDE 10

Early Prototyping and Analysis

2009-4-12 ISPD 2009

Prototyping

  • Grid and pad exploration
  • Package planning
  • Switch and pad planning
  • Decap strategy

Prototyping

  • Grid and pad exploration
  • Package planning
  • Switch and pad planning
  • Decap strategy

Implementation

  • Partial design information
  • Early dynamic and Chip-

Power Model (CPM)

  • Significantly improve time-to-

result

Implementation

  • Partial design information
  • Early dynamic and Chip-

Power Model (CPM)

  • Significantly improve time-to-

result Generate grid Define “regions” Voltage/current Maps

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SLIDE 11

Early Analysis Options

2009-4-12 ISPD 2009

Prototyping

Excel2IR, Power-Grid Plan

Early Static

EM checks, Pad placement

Early Dynamic

Multi-state multi-cycle analysis

Early Chip Power Model

Early Package Design

Early Grid-Check

Power routing, Robustness checks

Extensive capabilities to design and prototype power grid Different types

  • f analysis to

design and verify system power integrity

Switch/Pad planning

Design, placement, count

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SLIDE 12

How does it work?

2009-4-12 ISPD 2009

Prototyping Flow Prototyping Flow

Tape Out P&R Front End

  • 1. Define your floorplan (REGIONs)
  • 2. Define associated power
  • 3. Define your PG grid
  • 4. Define the PG Pads

⇒ Run your Static Analysis

  • 5. Define Frequencies or Current profile
  • 6. Assign On-Die Decoupling

⇒ Run your Dynamic Analysis

vdd vdd gnd gnd

Watt Watt Watt Watt Watt Watt

FAO What If? FAO What If?

Project’s Time Line

time

Current

time

Current

time

Current

Watt

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SLIDE 13

Power Distribution

Distribute user input power uniformly over user

specified regions and/or over user specified IP/blocks

Static: use DC current Dynamic:

Triangular waveforms User specified PWL waveforms Transistor-level simulation waveforms

2009-4-12 ISPD 2009

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SLIDE 14

Option 1

Region E – User

specified region. User specified power for this region to be distributed uniformly over power routes in the area

2009-4-12 ISPD 2009

Region E

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SLIDE 15

Option 2

When pin view (LEF)

  • r detailed view

(routing) is not available.

Distribute power over

top level routes over a block.

2009-4-12 ISPD 2009 Blk b

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SLIDE 16

Option 3

When LEF pin view

available but detailed view (routing) not available.

Distribute power

uniformly over pins based on their connectivity to the top routing.

2009-4-12 ISPD 2009 Blk a

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SLIDE 17

Option 4

Blk c: hierarchical

block with routing

Sub blk cc: sub-block

with routing

Assign power to

routing inside block or sub-block based on layer specification.

2009-4-12 ISPD 2009 Blk c Sub-blk cc

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SLIDE 18

Power Grid Prototyping

A simple & quick method for analyzing voltage

drop impact.

Grid creation Via dropping Pad placement Switch insertion

2009-4-12 ISPD 2009

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SLIDE 19

Prototyping Example

Define regions and distribute power

2009-4-12 ISPD 2009

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SLIDE 20

Prototyping Example (Cont’d)

Create mesh for internal power domain

2009-4-12 ISPD 2009

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SLIDE 21

Prototyping Example (Cont’d)

Create mesh for external power domain

2009-4-12 ISPD 2009

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SLIDE 22

Prototyping Example (Cont’d)

Create mesh for ground domain

2009-4-12 ISPD 2009

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SLIDE 23

Prototyping Example (Cont’d)

Add pads

2009-4-12 ISPD 2009

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SLIDE 24

Prototyping Example (Cont’d)

Insert switches

2009-4-12 ISPD 2009

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SLIDE 25

Grid Connectivity Checks

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GridCheck

Connectivity checks Normalized or effective

GridCheck

Connectivity checks Normalized or effective

Missing Vias

Stacked or layer by layer Filtered by user constraints

Missing Vias

Stacked or layer by layer Filtered by user constraints

Shorts / Unconnects

Analysis w/ unclean layout List of shorts / opens

Shorts / Unconnects

Analysis w/ unclean layout List of shorts / opens vs s m 1 vdd m1 via2 m1 vdd missing via2

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SLIDE 26

Static Analysis

R network extraction DC simulation

2009-4-12 ISPD 2009

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SLIDE 27

Static Analysis Results: IR Map

External Power

Domain

Internal Power

Domain

Ground Domain

2009-4-12 ISPD 2009

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SLIDE 28

Dynamic Analysis

RC/RLC network extraction User provides current profiles (optional) User provides timing windows for switches

(low-power design)

Transient simulation

2009-4-12 ISPD 2009

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SLIDE 29

Dynamic Results: IR Map

External Power

Domain

Internal Power

Domain

Ground Domain

2009-4-12 ISPD 2009

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SLIDE 30

Switch Optimization Problems

Power switch placement Power switch sizing Power switch removal

Specify constraint as voltage drop on switch Based on static analysis result Remove redundant switches as many as possible

Power switch ramp-up scheduling

2009-4-12 ISPD 2009

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SLIDE 31

Switch Removal Example

Nominal voltage: 1.08V Before removal

Switch number: 312 Maximal voltage drop across switch: 3.512mV Minimal voltage drop across switch: 0.234mV Average voltage drop across switch: 1.393mV Worst voltage drop in internal net:

4.405mV(0.407%)

2009-4-12 ISPD 2009

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SLIDE 32

Switch Removal Result

2009-4-12 ISPD 2009

IR-drop Constraint On switch Removed Switches Number Area/ Leakage Reduction

  • Max. IR

Switch (mV)

  • Min. IR

Switch (mV)

  • Avg. IR

Switch (mV)

  • Wst. IR

Internal Net (mV)

3.52mV 11 3.52% 3.512 0.354 1.443 4.405 4mV 173 55.4% 3.799 2.596 3.103 5.315 5mV 203 65.1% 4.902 3.153 3.953 7.941 6mV 212 67.9% 5.727 3.425 4.307 22.51 N/A N/A N/A 3.512 0.234 1.393 4.405 After Removal Before Removal

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SLIDE 33

Switch Removal Result

2009-4-12 ISPD 2009

Initial IR Map IR Map with constraint = 4mV

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SLIDE 34

Why Early CPM?

CPM is a compact and accurate SPICE model

for the full-chip power distribution network

CPM can be seamlessly integrated for

package/board co-design

Early CPM helps in pad placement planning

and early package selection

Different types of CPM can be generated

DC current model (static analysis) Spatial and temporal current model (dynamic

analysis)

2009-4-12 ISPD 2009

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SLIDE 35

CPM Equivalent Circuit for Flip Chip

2009-4-12 ISPD 2009

Current signature VDD (port 2) i

…

j Topology of Gij G12 VSS (port 1) G11 G22

Parasitic network

Two-port example shown for simplicity

Flip Chip Partitions Flip Chip Partitions 00 01 10 11

Vdd_00 Vss_00 2N Terminal SPICE Equivalent Circuit

CPM CPM

N = # of Partitions

Vdd_00 Vss_00

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SLIDE 36

How does it work?

2009-4-12 ISPD 2009

Prototyping Flow Prototyping Flow

Tape Out P&R Front End

  • 1. Define your floorplan (REGIONs)
  • 2. Define associated power
  • 3. Define your PG grid
  • 4. Define the PG Pads

⇒ Run your Static Analysis

  • 5. Define Frequencies or Current profile
  • 6. Assign On-Die Decoupling

⇒ Run your Dynamic Analysis ⇒ Create your 1st Chip Power Model ⇒ Time & Freq Domain Analysis

FAO What If? FAO What If?

Project’s Time Line

CPM CPM CPM CPM

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SLIDE 37

Early Analysis and CPM Flow

  • No package parasitic are used in

the simulation ( Chip power model is package independent)

  • No separate dynamic simulation

required

  • CPM internally performs dynamic

simulation for capturing the current signature

  • CPM dynamic simulation run

time might be higher than regular dynamic simulation time

2009-4-12 ISPD 2009

Setup Design Power Calculation PG Extraction CPM Creation

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SLIDE 38

Application of CPM in Global Power Integrity

Global PDN target impedance IC-Package resonance analysis Dynamic voltage noise budgeting at board and

package level

Package and board optimization System in package (SiP) EMI analysis

2009-4-12 ISPD 2009

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SLIDE 39

Summary

Early Static Analysis

Plan and verify power distribution network

Early Dynamic Analysis

Explore different scenarios

Transitions from one state to another Multi-cycle analysis

Early package design

Chip power model creation Package response for on-die current transition

2009-4-12 ISPD 2009

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SLIDE 40

Thank You!

2009-4-12 ISPD 2009