Programming Language Interface Sayed Amirhossein Mirhosseini Uses - - PowerPoint PPT Presentation
Programming Language Interface Sayed Amirhossein Mirhosseini Uses of PLI PLI can be used to define additional system tasks and functions e.g. monitoring tasks , stimulus tasks , PLI can be used to extract design information such
e.g. monitoring tasks , stimulus tasks , …
This software will work with all Verilog simulators
This process is called linking the PLI routines into the
Different simulators provide different mechanisms to
Module instances, module ports, module pin-to-pin paths,
Top-level modules Primitive instances, primitive terminals Nets, registers, parameters, specparams Integer, time, and real variables Timing checks Named events
Handles are predefined data types that point to
handle top_handle;
They return handles to objects in the design.
acc_handle_.
They return the handle to the next object in the set
acc_next_
They allow the user system task to add and delete
acc_vcl_
They can extract a variety of information about
acc_fetch_.
#include "acc_user.h" int get_ports() { handle mod, port; int input_ctr = 0; int output_ctr = 0; int inout_ctr = 0; acc_initialize(); mod = acc_handle_tfarg(1); /* get a handle to the module instance first argument in the system task argument list */ port = acc_handle_port(mod, 0); /* get the first port of the module */ while( port != null ) /* loop for all ports */ { if (acc_fetch_direction(port) == accInput) /* Input port */ { io_printf("Input Port %s \n", acc_fetch_fullname(port)); /* full hierarchical name */ input_ctr++; }
else if (acc_fetch_direction(port) == accOutput) /* Output port */ { io_printf("Output Port %s \n", acc_fetch_fullname(port));
} else if (acc_fetch_direction(port) == accInout) /* Inout port */ { io_printf("Inout Port %s \n", acc_fetch_fullname(port)); inout_ctr++; } port = acc_next_port(mod, port); /* go to the next port */ } io_printf("Input Ports = %d Output Ports = %d, Inout ports = %d\n\n", input_ctr, output_ctr, inout_ctr); acc_close(); }
module top; wire OUT; reg I0, I1, S; mux2_to_1 my_mux(OUT, I0, I1, S); /*Instantiatethe 2-to-1 mux*/ initial begin $get_ports("top.my_mux"); /*invoke task $get_ports to get port list*/ end endmodule
Output Port top.my_mux.out Input Port top.my_mux.i0 Input Port top.my_mux.i1 Input Port top.my_mux.s Input Ports = 3 Output Ports = 1, Inout ports = 0
#include "acc_user.h" int my_monitor() { handle net; char *netname ; /*pointer to store names of nets*/ char *malloc(); acc_initialize(); /*initialize environment*/ net = acc_handle_tfarg(1); /*get a handle to the net to be monitored*/ netname = malloc(strlen(acc_fetch_fullname(net))); strcpy(netname, acc_fetch_fullname(net)); /* Call the VCL routine to add a signal to the monitoring list*/ /* Pass four arguments to acc_vcl_add task*/ /* 1st : handle to the monitored object (net) 2nd : Consumer C routine to call when the object value changes (display_net) 3rd : String to be passed to consumer C routine (netname) 4th : Predefined VCL flags: vcl_verilog_logic or vcl_verilog_strength */ acc_vcl_add(net, display_net, netname, vcl_verilog_logic); acc_close(); }
typedef struct t_vc_record{ int vc_reason; /*reason for value change*/ int vc_hightime; /*Higher 32 bits of 64-bit simulation time*/ int vc_lowtime; /*Lower 32 bits of 64-bit simulation time*/ char *user_data; /*String passed as the argument of acc_vcl_add*/ union { /*New value of the monitored signal*/ unsigned char logic_value; double real_value; handle vector_handle; s_strengths strengths_s; } out_value; } *p_vc_record;
display_net(p_vc_record vc_record) { io_printf("%d New value of net %s is %c \n", vc_record->vc_lowtime, vc_record->user_data, convert_to_char(vc_record->out_value.logic_value)); }
char convert_to_char(char logic_val) { char temp; switch(logic_val) { case vcl0: temp='0'; break; case vcl1: temp='1'; break; case vclX: temp='X'; break; case vclZ: temp='Z'; break; } return(temp); }
module top; wire OUT; reg I0, I1, S; mux2_to_1 my_mux(OUT, I0, I1, S); //Instantiate the module mux2_to_1 initial //Add nets to the monitoring list begin $my_monitor("top.my_mux.sbar"); $my_monitor("top.my_mux.y1"); end initial //Apply Stimulus begin I0=1'b0; I1=1'b1; S = 1'b0; #5 I0=1'b1; I1=1'b1; S = 1'b1; #5 I0=1'b0; I1=1'b1; S = 1'bx; #5 I0=1'b1; I1=1'b1; S = 1'b1; end endmodule
Do long arithmetic Display messages Halt, terminate, save, and restore simulation …
1st Argument 2nd Argument Action none Stop simulation. Display simulation time and message. 1 none Finish simulation. Display simulation time and message. any value Stop simulation. Display simulation time, module instance from which stop was called, and message. 1 any value Finish simulation. Display simulation time, module instance from which stop was called, and message.
#include "veriuser.h" int my_stop_finish() { if(tf_nump() == 1) /* if 1 argument is passed , display only simulation time */ { if(tf_getp(1) == 0) /* if the argument is 0, then stop the simulation*/ { io_printf("Mymessage: Simulation stopped at time %d\n", tf_gettime()); tf_dostop(); /*stop the simulation*/ } else if(tf_getp(1) == 1) /* if the argument is 0 , terminate the simulation*/ { io_printf("Mymessage: Simulation finished at time %d\n“, tf_gettime()); tf_dofinish(); /*terminate the simulation*/ } else /* Pass warning message */ tf_warning("Bad arguments to \$my_stop_finish at time%d\n“,tf_gettime()); }
else if(tf_nump() == 2) /* if 1 argument is passed, print module instance and time*/ { if(tf_getp(1) == 0) /* if the argument is 0 then stop the simulation*/ { io_printf ("Mymessage: Simulation stopped at time %d in instance %s \n", tf_gettime(), tf_mipname()); tf_dostop(); /*stop the simulation*/ } else if(tf_getp(1) == 1) /* if the argument is 0 then terminate the simulation*/ { io_printf ("Mymessage: Simulation finished at time %d in instance %s \n", tf_gettime(), tf_mipname()); tf_dofinish(); /*terminate the simulation*/ } else /* Pass warning message */ tf_warning("Bad arguments to \$my_stop_finish at time %d\n",tf_gettime()); } }
module top; wire OUT; reg I0, I1, S; mux2_to_1 my_mux(OUT, I0, I1, S); //Instantiate the module mux2_to_1 initial //Apply Stimulus begin I0=1'b0; I1=1'b1; S = 1'b0; $my_stop_finish(0); //Stop simulation. Don't print module instance name #5 I0=1'b1; I1=1'b1; S = 1'b1; $my_stop_finish(0,1); //Stop simulation. Print module instance name #5 I0=1'b0; I1=1'b1; S = 1'bx; $my_stop_finish(2,1); //Pass bad argument 2 to the task #5 I0=1'b1; I1=1'b1; S = 1'b1; $my_stop_finish(1,1); //Terminate simulation. Print module instance //nameend endmodule
Output :