I/O Bus and Interface Data Bus Addr Bus CPU Control Interface - - PDF document

Flaxer Eli - Computer Architecture

Ch 8 - 1

I/O Bus and Interface

CPU Interface Keyboard & Display Interface Printer Interface Hard Disk Interface CD

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DVD

Data Bus Addr Bus Control

Flaxer Eli - Computer Architecture

Ch 8 - 2

Example: 8254

8254

CS RD WR

CPU

AB(2..9) IOR AB(1) IOW DB(0..7) DB A1 A0 AB(0)

Port Select

Timer 0 Timer 1 Timer 2 Status Control Base Port Address is: 0x40 Port Space is: 1024 ports

Flaxer Eli - Computer Architecture

Ch 8 - 3

8254 Control Field

SC1 SC0 Select Counter 0 1 Select Counter 1 1 Select Counter 2 1 1 Read - Back Command RW1 RW0 Counter Latch Command 1 Read / Write LSB 1 Read / Write MSB 1 1 Read / Write LSB first & MSB after SC - Select Counter RW - Read Write

Flaxer Eli - Computer Architecture

Ch 8 - 4

8254 Control Field

M2 M1 M0 Mode 0 1 Mode 1 1 Mode 2 1 1 Mode 3 1 Mode 4 1 1 Mode 5 BCD Binary Counter 16 Bit 1 BCD Counter 4 Digit M - Mode BCD - Binary Code Decimal

Flaxer Eli - Computer Architecture

Ch 8 - 5

Hardware Interrupt Procedure

CPU

DB INT INTA

Peripheral Device

INTA INT DB Interrupt Number Jump Address (Method 2) Opcode (Method 1) Absolute Address Interrupt Vector Addess of Sub0 Jmp Sub0 Addess of Ret Code Ret 1 1 Addess of Sub2 Jmp Sub2 2 2 Addess of Ret Code Ret * * Addess of Ret Code Ret * * Addess of Ret Code Ret 15 15

Flaxer Eli - Computer Architecture

Ch 8 - 6

Multi Interrupts Procedure

CPU

DB INT INTA

Device 0

INTA INT

PIC

DB INT INTA

Device 1

INTA INT

Device 2

INTA INT

Device 3

INTA INT IRQ0 IRQ1 IRQ2 IRQ3

Flaxer Eli - Computer Architecture

Ch 8 - 7

PIC 82C59

Flaxer Eli - Computer Architecture

Ch 8 - 8

DMA Controller

Data Bus Buffers

DMA Request To I/O Device

Address Register Count Register Control Register Address Buffers

Data Bus RD WR DMAR DMAA CS RS BR BG

Control Logic

INTR Address Bus DMA Ack

Internal Bus

Bus Request Bus Grant Interrupt Reg Select

Flaxer Eli - Computer Architecture

Ch 8 - 9

DMA Transfer