Probe Card System for DHP Chip Testing VXD Workshop, Wetzlar, - - PowerPoint PPT Presentation

probe card system for dhp chip testing
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Probe Card System for DHP Chip Testing VXD Workshop, Wetzlar, - - PowerPoint PPT Presentation

Probe Card System for DHP Chip Testing VXD Workshop, Wetzlar, February 4-6, 2013 H. Krger, Bonn University Motivation To/from DCD PXD modules are sensitive to single- (86 CMOS/HSTL) point-of-failure of the DHP 18x CMOS 64x HSTL 4x


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SLIDE 1

Probe Card System for DHP Chip Testing

VXD Workshop, Wetzlar, February 4-6, 2013

  • H. Krüger, Bonn University
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SLIDE 2

Motivation

  • PXD modules are sensitive to single-

point-of-failure of the DHP

  • Up to know very little statistics of the

DHP yield (+ flip chip mounting to wirebond adapters with low yield only)

  • Need to qualify ICs before flip-chip

mounting

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 2

DHP To/from DCD (86 CMOS/HSTL) To/from DHH (9x LVDS) To Switcher (4x LVDS)

4 x LVDS Gbit TX 4x LVDS 4x JTAG 18x CMOS 64x HSTL 4x JTAG

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SLIDE 3

DHP Chip Probing Prerequisites

  • What is needed:

– Needle card for solder bump probing – Test bench for DHP environment

  • IO signals from test system (DHH like)
  • DCD input/output emulation

– Test procedure to provide full coverage – Definition of cut parameters for chip classification

  • Design is based on DHP 0.2
  • DHPT 1.x will be pin compatible to DHP 0.2

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 3

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SLIDE 4

Probe Station

DHP Chip Probe Test System

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn

DHP test system (XUPV5 FPGA Board) Needle Card PCB Probe Needles

FPGA DCD emulation Sequencer r/b

Power Supply DHP

DAC

Infiniband Eth GPIB or USB JTAG

4

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SLIDE 5
  • 159 bumps need to be connected
  • Material: lead free, LTS
  • Pitch: 200µm (y), 180µm (x)
  • ~110µm diameter
  • Connections:

– JTAG (4x LVDS) – Timing (4x LVDS) – Data Link (1x CML) – Aux clock (2x LVDS) – SWITCHER (4x LVDS) – DCD out (8x 8 HSTL) – DCD in (8x 2 CMOS) – DCD timing (2x CMOS) – DCD JTAG – DCD_ref (analog) – Power (8x VSS, 4x VDD, 2x VDD_CML) – PLLxx2Fast – FrameSync – ResetB (CMOS) – Analog IO test signals

200µm 180µm 3685µm 3685µm

bumps to connect: 159 out of 296 VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn

  • 4
  • 3
  • 2
  • 1

1 2 3 Thousands Thousands

5

DHP test system FPGA

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SLIDE 6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 A no bump 180 540 900 1260 1620 1980 2340 2700 2 B 100 360 100 720 100 1080 100 1440 100 1800 100 2160 100 2520 100 3 C 180 200 540 200 900 200 1260 200 1620 200 1980 200 2340 200 2700 200 4 D 300 360 300 720 300 1080 300 1440 300 1800 300 2160 300 2520 300 5 E 180 400 540 400 900 400 1260 400 1620 400 1980 400 2340 400 2700 400 6 F 500 360 500 720 500 1080 500 1440 500 1800 500 2160 500 2520 500 7 G 180 600 540 600 900 600 1260 600 1620 600 1980 600 2340 600 2700 600 8 H 700 360 700 720 700 1080 700 1440 700 1800 700 2160 700 2520 700 9 J 180 800 540 800 900 800 1260 800 1620 800 1980 800 2340 800 2700 800 10 K 900 360 900 720 900 1080 900 1440 900 1800 900 2160 900 2520 900 11 L 180 1000 540 1000 900 1000 1260 1000 1620 1000 1980 1000 2340 1000 2700 1000 12 M 1100 360 1100 720 1100 1080 1100 1440 1100 1800 1100 2160 1100 2520 1100 13 N 180 1200 540 1200 900 1200 1260 1200 1620 1200 1980 1200 2340 1200 2700 1200 14 O 1300 360 1300 720 1300 1080 1300 1440 1300 1800 1300 2160 1300 2520 1300 15 P 180 1400 540 1400 900 1400 1260 1400 1620 1400 1980 1400 2340 1400 2700 1400 16 Q 1500 360 1500 720 1500 1080 1500 1440 1500 1800 1500 2160 1500 2520 1500 17 R 180 1600 540 1600 900 1600 1260 1600 1620 1600 1980 1600 2340 1600 2700 1600 18 S 1700 360 1700 720 1700 1080 1700 1440 1700 1800 1700 2160 1700 2520 1700 19 T 180 1800 540 1800 900 1800 1260 1800 1620 1800 1980 1800 2340 1800 2700 1800 20 U 1900 360 1900 720 1900 1080 1900 1440 1900 1800 1900 2160 1900 2520 1900 21 V 180 2000 540 2000 900 2000 1260 2000 1620 2000 1980 2000 2340 2000 2700 2000 22 W 2100 360 2100 720 2100 1080 2100 1440 2100 1800 2100 2160 2100 2520 2100 23 X 180 2200 540 2200 900 2200 1260 2200 1620 2200 1980 2200 2340 2200 2700 2200 24 Y 2300 360 2300 720 2300 1080 2300 1440 2300 1800 2300 2160 2300 2520 2300 25 Z 180 2400 540 2400 900 2400 1260 2400 1620 2400 1980 2400 2340 2400 2700 2400 26 AA 2500 360 2500 720 2500 1080 2500 1440 2500 1800 2500 2160 2500 2520 2500 27 AB 180 2600 540 2600 900 2600 1260 2600 1620 2600 1980 2600 2340 2600 2700 2600 28 AC 2700 360 2700 720 2700 1080 2700 1440 2700 1800 2700 2160 2700 2520 2700 29 AD 180 2800 540 2800 900 2800 1260 2800 1620 2800 1980 2800 2340 2800 2700 2800 30 AE 2900 360 2900 720 2900 1080 2900 1440 2900 1800 2900 2160 2900 2520 2900 31 AF 180 3000 540 3000 900 3000 1260 3000 1620 3000 1980 3000 2340 3000 2700 3000 32 AG 3100 360 3100 720 3100 1080 3100 1440 3100 1800 3100 2160 3100 2520 3100 33 AH 180 3200 540 3200 900 3200 1260 3200 1620 3200 1980 3200 2340 3200 2700 3200 34 AJ 3300 360 3300 720 3300 1080 3300 1440 3300 1800 3300 2160 3300 2520 3300 35 AK 180 3400 540 3400 900 3400 1260 3400 1620 3400 1980 3400 2340 3400 2700 3400 36 AL 3500 360 3500 720 3500 1080 3500 1440 3500 1800 3500 2160 3500 2520 3500 37 AM 180 3600 540 3600 900 3600 1260 3600 1620 3600 1980 3600 2340 3600 2700 3600

  • Bump coordinates in µm
  • Origin in upper left corner
  • No bump at location (0,0)
  • Bumps with no needle

connection shown in gray

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 6

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SLIDE 7

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn

DHP 0.2 Layout Examples from vendor

8

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SLIDE 8

Debug Probe Card

  • PCB with active components, will need

some debugging

  • Very sensitive with needles attached

 Dedicated debug “Probe” Card

  • (almost) same netlist as needle card PCB
  • replace needle footprint with DHP 0.2

wire bond adapter  Debug PCB is ready and tested

  • DHP communication 
  • FPGA programming (DCD emulation,

Switcher sequencer read-back) 

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn

Debug Probe Card

9

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SLIDE 9

Needle Card PCB

Specs

  • 6 layer PCB
  • 3mm thick  mechanical stiffness

Status

– PCB Design & Production  – Component mounting  – Testing  – Needle mounting

  • needs ~4 weeks (@ HTT)

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn

Needle Probe Card (w/o needles)

10

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SLIDE 10

Probe Station Setup

  • Needle card fixture 
  • We have diced chips only

– put single chips on chuck (Ok for now) – “chess board” fixture with array of cavities for production testing  tbd

  • External components:

– Power supply  – DHP test system (FPGA board via Infiniband cables)  – extra JTAG for on board FPGA programming/readback , optional: can use JTAG from Infiniband connection 

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 11

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SLIDE 11

Probe Card System Status

  • Hardware components of the needle card test system

– Debug probe card for HW verification and debugging  – Needle probe card: components mounted and tested, shipped for needle mounting end

  • f January (takes ~4 weeks)

– Mechanical fixture for probe station 

  • Software

– based on DHP test system from Mikhail () – needs further extensions (for basic testing ok)

  • (more) systematic sequencer and DHP DAC output read-back
  • automation of test sequences
  • coverage…
  • definition of cut parameters
  • Planning

– Start commissioning of the needle card system by end of Feb – First (rudimentary) tested DHP chips supposed to be available in March

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 12

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SLIDE 12

DHP Chip Availability

  • Only small number of DHP 0.2 chips left (~15)
  • Next chip version (DHPT 1.0) available by mid 2013
  • Need certain number of tested chips for E-MCM and PXD6 large matrix assemblies

Possible scenarios: a) DHP has high yield, enough Ok tested die for E-MCM + PXD6 (very optimistic)

 no action needed

b) DHP yield not sufficient, need more chips (more likely)

i) Buy remaining MPW chips from MOSIS (rather expensive) ii) Wait for DHPT 1.0 to become available (maybe too late) iii) Recover unsuccessful DHP 0.2 flip chip assemblies (quite a few)

 Recovery procedure

  • De-solder and clean DHP chips (Valencia ?)
  • Place new bumps (Heidelberg ?)

VXD Workshop, Wetzlar, Feb. 2013, H. Krüger, Uni Bonn 13