pre knowledge in order to complete this lab you will need
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Pre-Knowledge In order to complete this lab - PDF document

Pre-Knowledge In order to complete this lab you will need an understanding of what an Arithmetic logic unit (ALU) is. Pre-Lab Type out a short paragraph of 100 words approximately about what an


  1. ����������������� Pre-Knowledge In order to complete this lab you will need an understanding of what an Arithmetic logic unit (ALU) is. Pre-Lab Type out a short paragraph of 100 words approximately about what an ALU is. You can use any source. Objective In this lab, we learn to design a 1 bit ALU and then extend this design to a 16 bit ALU. Lab Execution Guidelines : For each lab there will be a report. This report will consist of a text that follows the report guideline, your code file, and screenshots of your working code. These files should be placed together in a single file, printed, and then turned into your TA. Your lab report is due the week after you finish lab. The lab is composed of a report worth 70 points (20 from the report and 50 for the vhdl files) and possibly a pre-lab worth 30 points. On labs that take place over multiple weeks there will be only a single lab report due the week after the lab is completed. Lab reports suffer a 10% per day overall penalty for late work. Tools: Xilinx ISE. If you have forgotten how to use ISE please review lab 1. VHDL Programming & Testing instructions: For this lab your first goal is to create a 1-bit ALU based on the full adder you have built on Lab2. Our ALU will have addition, subtraction, Logical AND and Logical OR functionality. Once finished, you will use the 1-bit ALU as a Module to create a 16 bit ALU. Finally, you have to test the ALU by writing a test bench that goes through each case presented at the end of this lab.

  2. The functionality of the ALU is determined by its select signals. The mapping from select to functionality should be as follows. S1 S0 Function 0 0 Add 0 1 Sub 1 0 And 1 1 Or Once you have built and tested your 1-bit ALU, then you should create a 16 bit ALU (using the same concepts you applied to create a 4 bit ripple carry adder in Lab 2).

  3. How to do the subtraction: Modify the 1 Bit ALU structure; add a XOR logic to input B for the Subtraction.

  4. Test the value in the table below and write the result in your report!!! S1 S0 A B Sout Cout 0 0 100 230 0 0 -20 60 0 0 1 1 0 1 500 340 0 1 55 70 0 1 -1 14 1 0 128 512 1 0 3000 2 1 0 5342 978 1 1 16 8 1 1 0 2345 1 1 -1 5

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