Power Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale - - PowerPoint PPT Presentation

• Power

Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel

Introduction to Digital VLSI Design

• ונכתלאובמ

VLSIיתרפס

• Why Low-Power Devices?

Practical reasons (Reducing power requirements of high throughput portable applications) Financial reasons (Reducing packaging costs and achieving memory savings) Technological reasons (Excessive heat prevents the realization of high density chips and limits their functionalities)

• Application Fields

Portable Electronics (PC, PDA, Wireless) IC Cost (Packaging and Cooling) Reliability (Electro migration) Signal Integrity (Switching Noise, DC Voltage Drop) Thermal Design Ultra-low-power applications Space missions (miniaturized satellites)

• Design Technology Trend

• Energy Distribution

50 100 150 200 250 0.25 0.18 0.13 0.1 0.07

Technology Power

Dynamic Power Static Power

• Driving Forces for Low-Power:

Deep-Submicron Technology

ADVANTAGES

Smaller geometries Higher clock

frequencies DISADVANTAGES

× Higher power

consumption

× Lower reliability

• Driving Forces for Low-Power:

Battery Limitations

Battery maximum power and capacity increases 10%-15% per year Increasing gap with respect to power demand

• What has worked up to now?

Voltage and process scaling Design methodologies

Power-aware design flows and tools, trade area for

lower power

Architecture Design Power down techniques

Clock gating, dynamic power management

Dynamic voltage scaling based on workload Better cell library design and resizing methods

• Cap. reduction, threshold control, transistor layout

• Opportunities for Power

Savings

• Power Metrics

Average power: Related to battery lifetime. Peak power: Related to reliability and thermal failure RMS power: Related to cycle-by-cycle power Energy=power × × × × time: Related to power-delay product. t P(t) Peak power Energy Average power RMS power

• Sources of Power

Consumption in CMOS

• Power Dissipation in CMOS

Circuits

Ptotal = Pswitching + Pshort-circuit + Pleakage

• %75

%5 %20

• Dynamic Power Consumption

Average power consumption by a node cycling at each period T:

(each period has a 0→1 or a 1 →0 transition)

CLK DD cycle switching

f V C T E P

battery

2

= =

CLK DD switching

f V C P

battery

2

α =

Average power consumed by a node with partial activity

(only a fraction α of the periods has a transition)

• Dynamic Power Consumption

Define effective capacitance Ceff: To minimize switching power

Reduce VDD Reduce Ceff

C Ceff α =

CLK DD eff switching

f V C P

inverter

2

2 1 =

CL = Ceff

• Power Dissipation in CMOS

Circuits

Ptotal = Pswitching + Pshort-circuit + Pleakage

• %75

%5 %20

• Power Dissipation due to

Short Circuit Currents

Short circuit current flows when both devices are on simultaneously:

p n

Th DD in Th

V V V V − < <

Short circuit current, Isc, flows from VDD to ground The power dissipated by a CMOS gate due to short circuit current is

DD SC circuit short

V I P =

−

• Power Dissipation due to

Short Circuit Currents

because both transistors will never be on simultaneously

p n

Th Th DD

V V V + <

Isc is significant when the input rise-fall time is much larger than the output rise-fall times. When input and output rise-fall times are equal, Isc tends to zero Isc =0 when

• Power Dissipation due to

Short Circuit Currents

If the current isc(t) is a triangle, then

( )

dt V t i E

t t DD SC circuit short

∫

=

−

2 1

The energy dissipated by a CMOS gate due to short circuit current is

( )

DD circuit short DD circuit short

V I P t t V I E

ave

max 1 2 max

5 . 5 . = − =

− −

• Power Dissipation due to

Short Circuit Currents

Short circuit component of the total power consumption may be important and may increase while scaling Short circuit power increases with signal transition times at inputs Short circuit power decreases with signal increasing load capacitance (because Imax decreases)

• Power Dissipation in CMOS

Circuits

Ptotal = Pswitching + Pshort-circuit + Pleakage

• Power Dissipation due to

Leakage Currents

Leakage currents are important in the systems with long periods of inactivity

Reverse bias diode current through the transistor

drain= IL

Subthreshold current through the channel of an off

transistor= Ids

( )

DD ds L leakage

V I I P + =

• Power Reduction Methods:

Voltage Supply Scaling

Historically most adapted method is the reduction of voltage supply, VDD

CLK DD eff switching

f V C P

2

2 1 =

• Power Reduction Methods:

Voltage Supply Scaling

Gate delay, Td, increases as VDD decreases! ⇒The circuit cannot be switched very fast!

• Additional Power Reduction

Methods

Preserving circuit speed and computational throughput mandatory. Two solutions:

Threshold voltage scaling Architecture driven voltage scaling based

• n

Pipelining Parallelization

• Power Reduction Methods:

Threshold Voltage Scaling

Reduce threshold voltage while reducing supply voltage: Example:

Circuit A: VDD=1.5V, VTh=1V Circuit B: VDD=0.9V, VTh=0.5V

Circuits A and B approximately have the same performance

• Other Methods in Power

Reduction

• Supply voltage scaling is not the only

possible solution to reduce power consumption.

• Considerable results can be obtained through

minimization of Ceff.

• Ceff is proportional to switching= Ceff= ∝CL
• Design and synthesis techniques have been

developed to reduce both the capacitive Ioad, CL and the switching activity, ∝, at all stages

• f the design process.

• Power Analysis

Fast and accurate analysis in the design process

Power budgeting Knowledge-based architectural and

implementation decisions

Package selection Power hungry module identification

Detailed and comprehensive analysis at the later stages

Satisfaction of power budget and constraints Hot spots

• Low Power Design

Reduce dynamic power

α: clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency

Reduce static power

Selectively use ratioed circuits Selectively use low Vt devices Leakage reduction:

stacked devices, body bias, low temperature

• Concept

Ptoral = PLeakage + PSwitching + Psc