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Power Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale - PowerPoint PPT Presentation

Introduction to Digital VLSI Design VLSI Power Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale Semiconductors Israel


  1. Introduction to Digital VLSI Design VLSI יתרפס� � ��ונכתל�אובמ Power Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel �������� ����������������������������

  2. Why Low-Power Devices? Practical reasons (Reducing power requirements of high throughput portable applications) Financial reasons (Reducing packaging costs and achieving memory savings) Technological reasons (Excessive heat prevents the realization of high density chips and limits their functionalities) �������� ����������������������������

  3. Application Fields Portable Electronics (PC, PDA, Wireless) IC Cost (Packaging and Cooling) Reliability (Electro migration) Signal Integrity (Switching Noise, DC Voltage Drop) Thermal Design Ultra-low-power applications Space missions (miniaturized satellites) �������� ����������������������������

  4. Design Technology Trend �������� ����������������������������

  5. Energy Distribution 250 200 Power 150 Dynamic Power Static Power 100 50 0 0.25 0.18 0.13 0.1 0.07 Technology �������� ����������������������������

  6. Driving Forces for Low-Power: Deep-Submicron Technology ADVANTAGES DISADVANTAGES × Higher power � Smaller geometries consumption � Higher clock × Lower reliability frequencies �������� ����������������������������

  7. Driving Forces for Low-Power: Battery Limitations Battery maximum power and capacity increases 10%-15% per year Increasing gap with respect to power demand �������� ����������������������������

  8. What has worked up to now? Voltage and process scaling Design methodologies � Power-aware design flows and tools, trade area for lower power Architecture Design Power down techniques � Clock gating, dynamic power management Dynamic voltage scaling based on workload Better cell library design and resizing methods � Cap. reduction, threshold control, transistor layout �������� ����������������������������

  9. Opportunities for Power Savings �������� ����������������������������

  10. Power Metrics Average power: Related to battery lifetime. Peak power: Related to reliability and thermal failure RMS power: Related to cycle-by-cycle power Energy=power × × time: Related to power-delay × × product. Peak power P(t) RMS power Average power Energy t �������� ����������������������������

  11. Sources of Power Consumption in CMOS �������� ����������������������������

  12. Power Dissipation in CMOS Circuits P total = P switching + P short-circuit + P leakage ���������������� ������� ������� ���������������� ������� �������� ���������� ����� ����������� ��������������� ����������� ������������ %75 %20 %5 �������� ����������������������������

  13. Dynamic Power Consumption Average power consumption by a node cycling at each period T : (each period has a 0 → 1 or a 1 → 0 transition) E cycle = = P C V f 2 switching DD CLK T 0 battery Average power consumed by a node with partial activity (only a fraction α of the periods has a transition) = α P C V f 2 switching DD CLK 0 battery �������� ����������������������������

  14. Dynamic Power Consumption Define effective capacitance C eff : = α C eff C 0 1 = P C V f 2 switching eff DD CLK inverter 2 To minimize switching power � Reduce V DD C L = C eff � Reduce C eff �������� ����������������������������

  15. Power Dissipation in CMOS Circuits P total = P switching + P short-circuit + P leakage ���������������� ������� ������� ���������������� ������� �������� ���������� ����� ����������� ��������������� ����������� ������������ %75 %20 %5 �������� ����������������������������

  16. Power Dissipation due to Short Circuit Currents Short circuit current flows when both devices are on simultaneously: < < − V V V V Th in DD Th n p Short circuit current, I sc , flows from V DD to ground The power dissipated by a CMOS gate due to short circuit current is = P I V − short circuit SC DD �������� ����������������������������

  17. Power Dissipation due to Short Circuit Currents I sc is significant when the input rise-fall time is much larger than the output rise-fall times. When input and output rise-fall times are equal, I sc tends to zero I sc =0 when < + V V V DD Th Th n p because both transistors will never be on simultaneously �������� ����������������������������

  18. Power Dissipation due to Short Circuit Currents The energy dissipated by a CMOS gate due to short circuit current is t ( ) ∫ = E i t V dt 2 − short circuit SC DD t 1 If the current i sc (t) is a triangle, then ( ) = − E I V t t 0 . 5 − short circuit DD max 2 1 = P I V 0 . 5 − short circuit DD max ave �������� ����������������������������

  19. Power Dissipation due to Short Circuit Currents Short circuit component of the total power consumption may be important and may increase while scaling Short circuit power increases with signal transition times at inputs Short circuit power decreases with signal increasing load capacitance (because I max decreases) �������� ����������������������������

  20. Power Dissipation in CMOS Circuits P total = P switching + P short-circuit + P leakage ���������������� ������� ������� ���������������� ������� �������� ���������� ����� ����������� ��������������� ����������� ������������ �������� ����������������������������

  21. Power Dissipation due to Leakage Currents Leakage currents are important in the systems with long periods of inactivity � Reverse bias diode current through the transistor drain= I L � Subthreshold current through the channel of an off transistor= I ds ( ) = + P I I V leakage L ds DD �������� ����������������������������

  22. Power Reduction Methods: Voltage Supply Scaling Historically most adapted method is the reduction of voltage supply, V DD 1 = P C V f 2 switching eff DD CLK 2 �������� ����������������������������

  23. Power Reduction Methods: Voltage Supply Scaling Gate delay, T d , increases as V DD decreases! ⇒ The circuit cannot be switched very fast! �������� ����������������������������

  24. Additional Power Reduction Methods Preserving circuit speed and computational throughput mandatory. Two solutions: � Threshold voltage scaling � Architecture driven voltage scaling based on � Pipelining � Parallelization �������� ����������������������������

  25. Power Reduction Methods: Threshold Voltage Scaling Reduce threshold voltage while reducing supply voltage: Example: � Circuit A: V DD =1.5V, V Th =1V � Circuit B: V DD =0.9V, V Th =0.5V Circuits A and B approximately have the same performance �������� ����������������������������

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