Pixel Detector for the Protein Crystallography Beamline at the SLS - - PDF document

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pixel detector for the protein crystallography beamline
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Pixel Detector for the Protein Crystallography Beamline at the SLS - - PDF document

Jan 08, 2024 394 likes •586 views

Paul Scherrer Institut Pixel Detector for the Protein Crystallography Beamline at the SLS PSI Ch. Brnnimann 1 , E. Eikenberry 1 , S. Kohout 1 , B. Schmitt 1 , C. Schulze 1 , R. Baur 2 and R.Horisberger 2 1 Swiss Light Source, Paul Scherrer

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SLIDE 1

Pixel Detector for the Protein Crystallography Beamline at the SLS

Paul Scherrer Institut

  • Ch. Brönnimann, SLS
  • Ch. Brönnimann1, E. Eikenberry1, S. Kohout1, B. Schmitt1, C. Schulze1 ,
  • R. Baur2 and R.Horisberger2

1 Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen-PSI 2 CMS-Project, Paul Scherrer Institut, CH-5232 Villigen-PSI

PSI

  • P. Fischer3, S. Florin3 and M. Lindner3

3Physikalisches Institut der Universität Bonn,

Nussallee 12 D-53115 Bonn

University of Bonn

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SLIDE 2

λ θ = ⋅ ) sin( 2d

Beam Energy: 5-17.5 keV Intensity: ~10 /s Focal spot size: Adjustable to 25 x 15 m Divergency:150 µrad x 28 µrad (FWHM)

13 2

µ Crystal rotation

  • 30-180 degree for complete data set
  • Currently: Discrete rotation, integration
  • ver certain rotation angle
  • Future: Continuous rotation, integration

determined by detector frame rate ( ) Fine phi slicing Spot size:

  • Beam divergence
  • Mosaicity of the crystal
  • Distance sample-detector
  • Point spread function of detector

Diffraction data

  • reflect crystal symmetry group
  • orientation of the crystal-> orientation matrix
  • High dynamic range: >10 between strong and weak reflections
  • Intensities need to be determined accurately (1%)
  • Determination of amplitudes and phases leads

to electron density maps

4

Detector requirements:

  • Large area (40 x 40 cm ) and/or large number of pixels
  • Detect a high number of reflection orders (>500)
  • Accurate determination of integrated intensities
  • Wide dynamic range (>16 bit, i.e. single photon counting detector)
  • Fast readout (<0.1s)

2

θ

Resolution:

) sin( 2d

For d=1A and =1A, =60 λ θ

  • Crystallized

Protein X-ray Detector Diffraction pattern Diffracted beam

Beam

Data collection in protein crystallography

Paul Scherrer Institut

  • Ch. Brönnimann, SLS
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SLIDE 3

Pixel Detectors: Principle

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Pixel Sensor X-rays

Pixel Read-out Chip

0.2 mm 0.2 mm 0.3 mm

Bump Bonds Sensor Chip

Global Tresh

Treshold correction CS Amp Comp

Reset

Bump Pad

Enable/ Disable

  • +

Cal 1.7fF

Analog Block Digital Block

15 bit SR counter

Φ12 Clock Gen RBI RBO Ext Clock Ext/Comp Clock

Detector Pixel electronics

Radiation hard

n+ p+ n++ Al X-rays Edrift Vbias +

  • Si pn-junction

3.6 eV to create 1 eh-pair

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SLIDE 4

The SLS Pixel Detector

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

& Size: 40 x 40 cm2 (0.16m2) & 2000 x 2000 pixels & Pixel size: 200 x 200 µm2 & Modular detector -> dead area ~6% & High frame rate: >10Hz & High duty cycle: <6% (Tro~6ms) & In operation: 1.8.2001 (1000x1000)

Base plate (water cooled) Bank with 5 modules Modules with 16 chips

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SLIDE 5

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

SLS Pixel Module

Sensor Read-out chips Wire bonds High density flexible capton interconnect Base plate Al support Module Control Board MCB Cable

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SLIDE 6

Module Geometry

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

275 125 Sensor Pixels Chip Pixels 200 140

110 Readout chip Readout chip Readout chip Readout chip Sensitive Area 81.0 79.6 0.18 9.82 18.25 36.5 0.11 35.4 34

1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16

Horizontal Vertical Total Pixel size 0.2 0.2 mm 0.04 mm^2 Chip Nr of pixels 48 85 4080 Chip size 9.82 18.25 mm 179.215 mm^2 Sensor Nr of Pixels 398 170 67660 Nr of double pixels 14 170 2380 Sensor active area 79.6 34 2706.4 Module outside dim 81 36.6 mm 2964.6 mm^2

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SLIDE 7

Read-out electronics

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Main parameters

! Low noise analog block (ENC tot < 100 e-)

! Shaping time tsh = 100 ns -> 1MHz ! Radiation tolerant ! power consumption <100 µW/Pixel ! Robust comparator ! Individual threshold adjustment ! Low overall threshold variation (σ < 100e-) ! 15 bit pseudo random counter ! Large size (20 x 10 mm2)

Prototypes

Name Size Pixel Architecture Chip Architecture Subm. Receiv. SLS01 8x2 array Analog, comparator, counter

  • Dez 98

April 99 SLS02 22 x 30 Analog, comparator!, counter, trimbits Indiv. Coloumn architectur May 99 Nov 99 SLS03 1 x 90 As SLS02, final length column

  • Aug 99

Mar 00 SLS04 22 x 30 As SLS02 but with correct comparator As SLS02 Dez 99 Exp May 00 SLS05 30 x 30 As SLS04, improved trimbit mechanism

  • Indiv. Pixel

Architecture (Yield tolerant design) Feb 00 Exp July 00 SLS06 (Final chip) 48 x 85 As SLS05 As SLS05 Exp Oct 00 Exp Feb 01

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SLIDE 8

Pixel Layout

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Designed in radiation hard DMILL technology (R. Baur, Ch. Brönnimann) Size: 200 x 200 µm2 Low noise preamp (folded cascode) Bump Pad Shaper Threshold trimming (3 Bits) AC-coupled comparator 15 bit semi-static pseudo random counter+ control logic

Size 200 x 200 µm

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SLIDE 9
  • Ch. Brönnimann, SLS

Paul Scherrer Institut

SLS02 Architecture

TBI In CLK DIS

FF Shift

Shift Shift Shift

Shift Clock gen

TCL OUT TBO

ChipControl & & & & & & > > >

Clock Gen Clock Gen Clock Gen

Column Control Column Control Column Control

Analog 15Bit Counter Pad Pixel 30 Pixel1

DIS Mode Mode CLK CLK OUT

200f 100f 200f 1.5f 10f 20f

Pr

Sh Comp Mode Mode comp previous next clk Xor Clockgen Xor ds_shift ds_shift ds_shift ds_shift ds_shift ds_shift Phi1 Phi2 Bit1 Bit2 Bit3 Bit13 Bit14 Bit15 Icomp Vcal

LS

Pixel

+

Dis

Column1 Column22 DOUT

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SLIDE 10

Pixel: Preamp-Shaper

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

FC FB SF

FC=folded cascode SF=source follower FB=Feedback

Preamp Shaper

t ~30ns t ~60ns

peak shape

200f 80f 1.7f 10f 20f Shaper Comp

100f

Preamp I =I +I

comp c trim

Vcal

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SLIDE 11

SLS02 Analog Part Results

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

! Noise measurements (without detector): ENC ~50e- (P=75 µW/pixel, tsh = 100 ns) ! Amplification: ~60mV/1000e- ! Linearity limit: ~6000e (21keV)

y = 0.0564x + 18.14 50 100 150 200 250 300 350 400 450 1000 2000 3000 4000 5000 6000 7000

Analog out signal Calibration signal 100ns/div, Ch1: 100mV/div, Ch2: 50mV/div

Signal charge Analog Output [mV]

VRF\VRFS

  • 700
  • 600
  • 500
  • 400
  • 300
  • 200

300 96 71 63 74 45 70 200 95 69 61 56 50 77 100 96 82 67 75 64 78 120 98 100 75 83 100

  • 700
  • 600
  • 500
  • 400
  • 300
  • 200

300 100 20 40 60 80 100 120 100-120 80-100 60-80 40-60 20-40 0-20

Noise depence on feedback resistors settings

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SLIDE 12

Pixel: Comparator and trimming

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Vtrim

T1 T2 T3

100f I =5 A

b

µ I ~0.2 A

c

µ I ~1 A

c0

µ local global Threshold setting Inc Outc Dis Comp Level shift

AC-coupled comparator with diode feedback

  • simple inverter as comparator
  • comparator biasing done via pn-junction of the diode ->

expect lower threshold variations on the chip

  • radiation insensitive
  • low power consumption
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SLIDE 13

Comparator Results

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

! Minimum Threshold < 700e- ! Threshold variation: 130 e- untrimmed

Trimbits SLS04

100 200 300 400 500 600 700 800 900 1000 1100 1200 4.1 4.15 4.2 4.25 4.3 4.35 4.4 Vtrim [V] DVthr [e] Trim1 Trim2 Trim4 Trim7 Power

Threshold trimming: Very low trim currents

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SLIDE 14

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

SLS03: 2cm long column biased via periphery

AOUT of Pixel #18 and #90

  • 40
  • 20

20 40 60 80 100 120 140 160

  • 200

200 400 600 800 1000 1200 1400

time [ns] Amplitude [mV] Pixel 18 Pixel 90

1. supply in [V]

  • ut [V]

∆ [V] VD+ 5.025 4.81

  • 0.22

VD- 0.000 0.22 +0.22 VA+ 5.024 4.93

  • 0.09

VA- 0.000 0.10 +0.10 VSF- 1.012 1.14 +0.13 VC- 2.983 3.06 +0.08 VGND 3.741 3.50

  • 0.24

Vsh 3.741 3.74 ±0.00 Vg+ 5.024 4.92

  • 0.10

VC+ 5.024 4.95

  • 0.07

90 18 1 supplies

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SLIDE 15
  • Ch. Brönnimann, SLS

Paul Scherrer Institut

SLS05 Architecture

&

CTIN DIN DCLK EN CAL

FF Shift Shift

C 1 Φ CΦ2 DOUT AOUT CHSEL PSEL CTOUT

Chip Control >

R 1 Φ RTIN R 2 Φ RTOUT

Shift Shift Shift Shift Shift Shift

Pad

200f 200f 100f 1.5f 10f 30f

Pr

Sh Comp

RS&CS 0: Readout 1: Count clk comp Xor In Clockgen XOR shift shift shift shift shift shift shift shift Phi1 Phi2 Bit1 Bit2 Bit3 Bit4 Bit5 Bit15 Bit14 Bit13 Vcomp Vrfs Vrf

LS

+

Dis Trim bit 1 Trim bit 2

15-bit counter & & & Column Control

In Cal Clk Dis

Shift

VA- VD+

Row Control RS&CS

1: CS active 0: Selected pixel in cnt mode

CTOUT CTOUT PSEL CHSEL

CS Aout

{

PSEL

Pixel

CHSEL CHSEL + VC-

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SLIDE 16

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Final Chip: Yield estimation

Yield measurements of SLS02 chip (22x30 pixels): Defects due to dynamic logic (Semi-static SR in Pixels): 3.8x10-4 /bit -> 5.8x10-3/pixel (Yield for 85 pixel column: 60%) Defects in analog part: 3/19=0.842/chip Yield estimation for 48 x 85 pixel chip XY-Adressing, 133 SR-cells: 0.898 Analog part 0.346 30 bad pixels 0.916 Expected overall yield 0.28

Binomial Distribution

0.000E+00 2.000E-01 4.000E-01 6.000E-01 8.000E-01 1.000E+00 4045 4050 4055 4060 4065 4070 4075 4080 4085 Nr of Pixels working Probability

Sum

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SLIDE 17

Design of a large read-out chip for protein crystallography: Conclusions

Paul Scherrer Institut

  • Ch. Brönnimann, SLS

Prototype chips with 22x30 pixels are working Simulated final chip with one 20mm long column-> working Dynamic logic in DMILL is a yield killer Design with yield tolerant architecture is a must