Advanced Digital IC-Design Content What happens when μ 0.1 m technology is scaled? gy 9 nm Technology Scaling Gate Source Drain Gate Source Drain Substrate Substrate IC Design Space Progress: Described by Gordon Moore Moore’s law, formulated 1965 New technologies Traditional give a new design design space design space ”The complexity for The complexity for space space minimum component Complexity costs has increased at a rate of roughly a factor Speed of two per year” ” ”… no reason to believe no reason to believe New it will not remain nearly Design constant for at least 10 y Space t i l Power i years” b Area i x e l F Source: Electronics, Volume 38, Number 8, 19 April 1965 1
Moore’s Law: Processors Example: 30 nm Transistor Reformulated by Moore 1975 The # of transistors will be doubled every 18 th month Gate Source Drain + + n n - p substrat Source: Intel Intel 20 nm Transistor ITRS International Technology Roadmap for Semiconductors Semiconductors Estimate of future technologies in a 15 year perspective New estimate every second year New estimate every second year http: / / public.itrs.net/ 2
ITRS System Drivers Where are we in about 10 years? Channel length MPU (Micro Processor Unit) decrease by 7 SoC (System-on-Chip) ( y p) [ nm ] [ ] Oxide thickness Vi Virus 100 decrease by 5 - Multi technology (digital, analog, and mixed) Technology - High Performance (high speed) Protein - Low Power Thickness of a 10 Molecule few atoms 9 nm AM/ S (Analog & Mixed Signal) Oxide thickness Metal Oxid DRAM (Dynamic RAM) Halvledare DNA (semiconductor) 1 1 Molecule 0.4 nm Technology predictions from four scenarios Atom 0.1 2001 2003 2005 2007 2010 2013 2016 Source: ITRS 2002 Update (High performance logic technology) Gate Oxide in an 150 nm technology Manufacturing: A lithographic process Photographic glass plate (mask) Polysilicon Gate Each layer is Gate Oxide projected to the silicon die Silicon crystal Dimensions close to light g wavelengths Out of reach for the About 10 molecular layers of SiO 2 Optics!!! 3
Manufacturing: A lithographic process Optical Proximity Correction (OPC) Line widths smaller than the wavelength of light Predistortion of the mask layout is needed when scaling down the technology OPC Corrections OPC Corrections No OPC With OPC Original Layout Needed for 0.1 micron and less Manufacturing: A lithographic process Power Consumption Painting a 1 cm line with a 3 cm brush… Two major types Dynamic power consumption - Two types Static power consumption Static power consumption - Traditionally two major types - Four in submicron technologies Courtesy : IBM 4
Current Spikes (Short Circuit) What Happens with the Power Consumption? Previous focus: Dynamic Current peak when both N- and V DD charging/ discharging of the g g g g PMOS are open load Charge Power consumption: V DD -V T 2 f P = C L V DD V T Discharge 80-90% from the load and 10-20% from other sources I peak N open P open Dynamic Power Consumption Why do the Static Power Increase? Lower threshold voltage V T to increase the “gate overdrive” 90% capacitive switching and 5 [V] That is to keep a reasonable propagation delay That is, to keep a reasonable propagation delay 5 10% short circuit power 10% h t i it 4 1.2 Distance 3 between V DD Short circuit power will decrease V DD 1 and V T will V DD in submicron technologies when 2 decrease age (V) 0.8 V DD gets closer to V T (Close to Zero 1 V T 0.93V 0.93V 0.75V 0.75V 0.6 when V DD =2V T ) when V =2V ) Volta 0.4 Gate Overdrive 1.4 1.0 0.8 0.6 0.35 0.25 0.18 ( V DD – V T ) Technology [μ m] 0.2 V T 0 2005 2006 2007 2008 2009 2010 2011 2012 Source: ITRS 5
Scaling & Static Power Consumption Dynamic vs. Static Power V DD -V T trade-off Static power is a large contributor to the power today Estimated to be about equal in today’s technologies New Technologies require reduced V DD 100 Require lower V T L V DD V T I off - (or slow devices) Dynamic power alized power [V] [V] [um] [pA] 1 High Leakage 3.3 0.58 0.35 1 65 nm Mainly 0.01 2.5 0.47 0.25 10 subthreshold Norma current 1.8 0.43 0.15 100 0.0001 in 65 nm Static power 1.6 0.4 0.10 1000 Year 0.0000001 1990 2000 2010 2020 Source: K. Roy Source: ITRS Most Important Leakage Currents Static Power in an NMOS Device Subthreshold dominates the power today Reverse-biased, drain and source to substrate Gate leakage will be the major source junction band-to-band-tunneling (BTBT) Leakage Gate oxide tunneling 1 uA Gate Leakage Subthreshold current Subthreshold Gate 6 orders of oxide 1 nA tunneling magnitude! g Junction BTBT Sub 1 pA Threshold Junction BTBT Junction BTBT 90 nm 50 nm 25 nm Source K. Roy, IEEE Micro, March – April 2006 Source K. Roy, IEEE Micro, March – April 2006 6
Gate Static Power in an NMOS Device Leakage Currents oxide tunneling Sub Threshold Leakage increase with temperature Junction BTBT Junction BTBT Subthreshold dominates at high temperatures Junction BTBT Major source in future technologies (25 nm) M j i f t t h l i (25 ) Leakage (A/ um 2 ) 15 nA Gate oxide tunneling Total Major source in future technologies (50 nm and 10 nA below) Note: Subthreshold Linear scale Subthreshold current 5 nA 5 nA Gate Leakage Major source today (90 and 65 nm) Junction BTBT and below at high operating temperatures 0 400 300 350 Temperature Source K. Roy, IEEE Micro, March – April 2006 Source K. Roy, IEEE Micro, March – April 2006 Why do the Static Power Increase? Why do the Static Power Increase? Gate Exponential increase of the Source Drain static power! Shrinking feature sizes, Shrinking thin oxide Shrinking thin oxide Thin oxide Low V T 10m ln (I D ) Lower voltage to avoid break-through High I off 100u Increased propagation delay t p : 1u V − V GS T = = × × × m v I I I I e e T 10n off ff C V 0 = t L DD 100p High V T p V T k V V 2 ( - ) Low I off 1p V GS (V) DD T 0 0.5 1.0 1.5 2.0 2.5 7
Gate Oxide Tunneling Normalized Gate Oxide Tunneling Experimental technology 90 nm technology Gate to bulk current High electrical field over the thin oxide ( t ox ) will High electrical field over the thin oxide ( t ) will cause tunneling through the gate Will be a major obstacle in submicron technologies Gate oxide tunneling tunneling C ox = 1.6 C ox = 1 Sub Threshold I gate-leak < 0.01 I gate-leak = 1 Junction BTBT Junction BTBT Other Static Power Consumption Static Power and Scaling Gate-Induced Drain Leakage (GIDL) Junction BTBT will increase Not very serious for the supply voltages Subthreshold current will increase gg y suggested by ITRS Gate oxide tunneling will increase Drain-Induced Barrier Lowering (DIBL) Result in an increase of the subthreshold current DIBL and GIBL give minor contributions Gate oxide Gate tunneling tunneling Source Drain DIBL Sub Threshold GIDL Junction BTBT Junction BTBT 8
Threshold Variations Device Variability – a big Problem Threshold voltage variations in 90 nm Leakage change exponentially with the threshold The problem increases with denser technologies Hotspots Scaling & Soft Errors Rate (SER) Cosmic Rays at Advanced tools to reduce the hotspot temperature ground level is about 15 Normalized Soft Error Rate times lower than in outer space Before After Noise margin decreases with lower V DD Mainly a memory problem (both SRAM and DRAM) Exponential growth with decreasing V DD Cosmic ray = high-energy particle from outer space 9
Some Quotations Full (ideal) Transistor Scaling Scaled device Cosmic rays are almost impossible to stop. They'll go Original device (New Technology) through 5 feet of concrete without any trouble … and cause a bit to flip (Lange IBM) V D V D /S t /S t ox /S t t ox I D /S In 0.13-micron technology we're seeing some memory Gate I D Gate technology with error rates of 10,000 or 100,000 FITs per Source Drain Source Drain megabit. This brings the frequency of error in a single device down to weeks or months (Eric-Jones MoSys) L L/S Channel length (L) Channel length (L/S) A system with 1 GByte of RAM can expect an error every y y p y Channel width (W) Channel width (W) Channel width (W/S) Channel width (W/S) two weeks; a hypothetical terabyte system would Thin oxide thickness (t ox ) Thin oxide thickness (t ox /S) experience a soft error every few minutes (Tezzaron Drain current (I D ) Drain current (I D /S) Voltage (V D , V T , V DD , etc.) Voltage (V D /S, V T /S, V DD /S, etc.) Semiconductor) Doping (N A ) Doping (SN A ) Increased acceptor concentration FIT/ Mbit = Failures In Time: Errors per billion hours of use for constant electrical field Scaling Factors: Area & Capacitance Scaling Factor: Delay ε ∝ × ∝ × × = × × W L W L C W L ox Area Capacitance ox t V ox W L C L 1 ∝ × ⇒ = Area Scaling factor S S S 2 = × Δ = − = Q C V C V V C V ε ( ) WL WL 1 ∝ × = × ⇒ = L OH OL L DD C ox Capacitance Scaling factor ox S S t S S 2 2 / = × = − × = − × Q I t k V V t k V V t ox 2 2 ( ) ( ) n GS T p H L n DD T pHL t ox C V W = t L DD ε = Material constant pH L − k V V 2 ( ) ox n D D T L 10
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