pipelining performance measurements
play

Pipelining Performance Measurements Cycle Time: Time in between - PowerPoint PPT Presentation

Mar 13, 2023 •325 likes •1.45k views

Pipelining Performance Measurements Cycle Time: Time in between clock ticks Latency: Time to finish a complete job, start to finish Throughput: Average jobs completed per unit time CyclesPerJob: Number of cycles between

  1. MEM IF ID WB or $s3, $s4, $t3 sw $s2, 0($t1) lw $s1, 0($t0) IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM or $s3, $s4, $t3 IF ID 1 2 3 4 5 6 7 8 Time->

  2. MEM IF ID WB or $s3, $s4, $t3 sw $s2, 0($t1) IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM 1 2 3 4 5 6 7 8 Time->

  3. MEM IF ID WB or $s3, $s4, $t3 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  4. MEM IF ID WB The machine in cycle 4 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  5. MEM IF ID WB The machine in cycle 5 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  6. In what cycle was $s1 written? In what cycle was $s4 read? In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  7. In what cycle was $s1 written? 6 In what cycle was $s4 read? In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1 , 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  8. In what cycle was $s1 written? 6 In what cycle was $s4 read? 5 In what cycle was the Add executed? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4 , $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  9. In what cycle was $s1 written? 6 In what cycle was $s4 read? 5 In what cycle was the Add executed? 3 IF ID MEM WB add $s0, $0, $0 IF ID MEM WB lw $s1, 0($t0) sw $s2, 0($t1) IF ID MEM WB or $s3, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  10. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete _______________, start to finish. • Throughput: Average ______________ completed per unit time. • Which is more important for reducing program execution time?

  11. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete instruction start to finish. • Throughput: Average ______________ completed per unit time. • Which is more important for reducing program execution time?

  12. Performance Analysis • Measurements related to our machine • Job = single instruction • Latency: Time to finish a complete instruction start to finish. • Throughput: Average number of instructions completed per unit time. • Which is more important for reducing program execution time?

  13. Pipelined Machine Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  14. Pipeline Registers • Named for two stages they separate • Store all data corresponding to lines that go through them w IF/ID w EX/MEM § 32b instruction § Zero § 32b nPC § 32b ALU result § 32b nPC w ID/EX § 32b register value § 32b register w MEM/WB § 32b register § 32b immediate field § 32b ALU result § 32b nPC § 32b memory value

  15. Register File • Only takes half of a cycle to read or write to register file • Convention: w Read 2nd half of cycle w Write 1st half of cycle

  16. Machine Comparison Fetch Decode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  17. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  18. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  19. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  20. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns

  21. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: 2.1*5=10.5 ns Throughput for machine: _____ inst/ns

  22. Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: 8 ns Latency of a single instruction: 8 ns Throughput for machine: 1/8 inst/ns Pipelined Implementation Clock cycle time: 2.1 ns Latency of a single instruction: 2.1*5=10.5 ns Throughput for machine: 1 / 2.1 inst/ns

  23. Example 2 – How do we speed up pipelined machine? Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  24. Example 2 – How do we speed up pipelined machine? Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Single cycle: 1 / 32 inst / ns Pipelined: 1 / 10.1 inst / ns

  25. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? _________ and _________

  26. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? Memory and _________

  27. Example 2 – Split more stages Fetch Decode Execute Memory Writeback 6ns 4ns 8ns 10ns 4ns 0.1 ns pipelined register delay Which stage(s) should we split? Memory and Execute

  28. Example 2 – After Split F D X1 X2 M1 M2 WB ___ns ___ns ___ns ___ns ___ns ___ns ___ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  29. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns ___ns ___ns ___ns ___ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  30. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns ___ns ___ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  31. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / ns Pipelined: 1 / ns

  32. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / 32 ns Pipelined: 1 / ns

  33. Example 2 – After Split F D X1 X2 M1 M2 WB 6 ns 4 ns 4 ns 4 ns 5 ns 5 ns 4 ns 0.1 ns pipelined register delay Single cycle: 1 / 32 ns Pipelined: 1 / 6.1 ns

  34. Incorrect Execution Easy Right? Not so fast. In what cycle does the add write $s0? In what cycle does the or read $s0? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  35. Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  36. Easy Right? Not so fast. In what cycle does the add write $s0 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 3 IF ID MEM WB WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  37. Easy Right? Not so fast. Ahhhh! Values can not pass backwards in time In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 3 IF ID MEM WB WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  38. Correct, Slow Execution Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  39. Only Register File rd/wr in half a cycle. All Correct, Slow Execution other stages take a full cycle – this is because of shared hardware Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  40. Barriers to pipelined performance • Uneven stages • Pipeline register delays

  41. Barriers to pipelined performance • Uneven stages • Pipeline register delays • Data Hazards

  42. Barriers to pipeline performance • Uneven stages • Pipeline register delays • Data Hazards w An instruction depends on the result of a previous instruction still in the pipeline

  43. Solutions? • What can we try to reduce data hazards or their effect?

  44. Default (do nothing): Stall Easy Right? Not so fast. In what cycle does the add write $s0? 1 st half of cycle 5 In what cycle does the or read $s0? 2 nd half of cycle 5 Stall - wasted cycles IF ID MEM WB add $s0, $0, $0 IF ID MEM WB or $s3, $s0, $t3 IF IF sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  45. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? In what cycle is $s0 used in the machine? IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  46. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? End of cycle 4 In what cycle is $s0 used ? IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  47. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? End of cycle 4 In what cycle is $s0 used ? beginning of cycle 4 IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  48. Solution 1: Data Forwarding In what cycle is $s0 calculated in the machine? end of cycle 4 In what cycle is $s0 used ? beginning of cycle 5 IF ID MEM WB lw $s0, 0($t4) IF ID MEM WB or $s3, $s0, $t3 ID sw $s2, 0($t1) IF ID MEM WB IF and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  49. Data-Forwarding Where are those wires? Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  50. Data-Forwarding Where are those wires? Decode Execute Memory Fetch << << 4 2 2 Addr Out Data src1 src1data op/fun PC Read Addr Out Data rs Data Memory src2 src2data Instruction rt Register File Memory rd destreg imm In Data destdata Sign 16 32 Ext (Writeback) Pipeline Register

  51. Data Forwarding Example 2 Draw the timing diagram with data forwarding Draw arrows to indicate data passing through forwarding lw $t0, 0($s0) F D M W addi $t0, $t0, 1 F D add $s2, $s2, $t0 F sw $s2, 0($s0) 1 2 3 4 5 6 7 8 9 10 11 12 Time->

  52. Solution 2: Instruction Reordering (Before reordering) Stall - wasted cycles IF ID MEM WB lw $s0, 0($t4) IF MEM WB or $s3, $s0, $t3 IF IF ID sw $s2, 0($t1) IF ID MEM WB and $s6, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

  53. Solution 2: Instruction Reordering (After Reordering) IF ID MEM WB WB lw $s0, 0($t4) IF ID MEM WB sw $s2, 0($t1) and $s6, $s4, $t3 IF ID MEM WB or $s3, $s0, $t3 IF ID ID MEM WB 1 2 3 4 5 6 7 8 Time->

  54. Who reorders instructions? • Static scheduling w Compiler w Simpler, but does not know when caches miss or loads/stores are to the same locations • Dynamic scheduling w Hardware w More complicated, but has all knowledge

  55. Solution 2: Instruction Reordering IF ID MEM WB WB lw $s0, 0($t4) IF ID ID MEM WB or $s3, $s0, $t3 sw $s3, 0($t1) IF ID MEM WB and $s0, $s4, $t3 IF ID MEM WB 1 2 3 4 5 6 7 8 Time->

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Pipelining Instruction Pipelining is the use of pipelining to allow more than one instruction to

Pipelining Instruction Pipelining is the use of pipelining to allow more than one instruction to

Pipelining Instruction Pipelining is the use of pipelining to allow more than one instruction to be in some stage of execution at the same time. Ferranti ATLAS (1963): Pipelining reduced the average time per instruction by

1.85k views • 147 slides
Pipelining Raul Queiroz Feitosa Parts of these slides are from the support material provided by

Pipelining Raul Queiroz Feitosa Parts of these slides are from the support material provided by

Pipelining Raul Queiroz Feitosa Parts of these slides are from the support material provided by W. Stallings Objective To present the Pipelining concept, its limitations and the techniques for performance optimization 2 Pipelining Outline

736 views • 30 slides
1 What Limits Performance? Stalls (Data Hazards) Data hazards Code Instruction depends on

1 What Limits Performance? Stalls (Data Hazards) Data hazards Code Instruction depends on

Instruction Scheduling Background: Pipelining Basics Last time Idea Register allocation Begin executing an instruction before completing the previous one Today Without Pipelining With Pipelining Instruction scheduling The

389 views • 7 slides
Unit 5: Pipelining Load-use stalling Pipelined multi-cycle operations Control hazards

Unit 5: Pipelining Load-use stalling Pipelined multi-cycle operations Control hazards

This Unit: Pipelining App App App Single-cycle &amp; multi-cycle datapaths System software Latency vs throughput &amp; performance Basic pipelining CIS 501: Computer Architecture Mem CPU I/O Data hazards Bypassing Unit

522 views • 24 slides
Basic Pipelining Wrap-up Exploiting ILP (from Slide Set 20) Chapter 6 and beyond 1 2

Basic Pipelining Wrap-up Exploiting ILP (from Slide Set 20) Chapter 6 and beyond 1 2

Slide Set #21: Basic Pipelining Wrap-up Exploiting ILP (from Slide Set 20) Chapter 6 and beyond 1 2 Pipelining Big Picture Remember the single-cycle implementation Improve performance by increasing instruction throughput

392 views • 5 slides
Lecture 2 (I ): Lecture 2 (I ): Pipelining &amp; Retiming Pipelining &amp; Retiming

Lecture 2 (I ): Lecture 2 (I ): Pipelining &amp; Retiming Pipelining &amp; Retiming

Lecture 2 (I ): Lecture 2 (I ): Pipelining &amp; Retiming Pipelining &amp; Retiming Hsie-Chia Chang E-mail : hcchang@mail.nctu.edu.tw Fall 2006 Outline Outline Pipelining of FI R Digital filters Data-Broadcast Structures

453 views • 28 slides
Chapter Six 1 2004 Morgan Kaufmann Publishers Pipelining The laundry analogy for

Chapter Six 1 2004 Morgan Kaufmann Publishers Pipelining The laundry analogy for

Chapter Six 1 2004 Morgan Kaufmann Publishers Pipelining The laundry analogy for pipelining: 2 2004 Morgan Kaufmann Publishers Pipelining Improve performance by increasing instruction throughput Single cycle 2400 ps

621 views • 41 slides
Midnight Laundry 2 Smarty Laundry 3 Pipelining Improve performance by increasing

Midnight Laundry 2 Smarty Laundry 3 Pipelining Improve performance by increasing

IC220 Set #19: Laundry, Co-dependency, and other Hazards of Modern (Architecture) Life Return to Chapter 4 1 Midnight Laundry 2 Smarty Laundry 3 Pipelining Improve performance by increasing instruction throughput Ideal speedup is

501 views • 15 slides
Computer Systems Lecture 15 Pipelining and Hazards CS 230 - Spring 2020 3-1 Pipelining CS

Computer Systems Lecture 15 Pipelining and Hazards CS 230 - Spring 2020 3-1 Pipelining CS

CS 230 Introduction to Computers and Computer Systems Lecture 15 Pipelining and Hazards CS 230 - Spring 2020 3-1 Pipelining CS 230 - Spring 2020 3-2 ISA Requirements for Pipelining Constant length instructions (fetch, decode)

628 views • 38 slides
Pipelining 1 Today Quiz Introduction to pipelining 2 Pipelining L L a a Logic

Pipelining 1 Today Quiz Introduction to pipelining 2 Pipelining L L a a Logic

Pipelining 1 Today Quiz Introduction to pipelining 2 Pipelining L L a a Logic (10ns) t t c c 10ns L L a a Logic (10ns) t t c c 20ns L L a a Logic (10ns) t t c c 30ns Whats the latency for one unit of

706 views • 27 slides
GaudiMP GaudiMP performance performance- and and KSM KSM- measurements measurements

GaudiMP GaudiMP performance performance- and and KSM KSM- measurements measurements

GaudiMP GaudiMP performance performance- and and KSM KSM- measurements measurements Nathalie Rauschmayr 1 Overview Overview 2 Speedup Speedup Reconstruction of 10000 Events 3 Speedup Speedup Simulation of 100 Events 4

344 views • 15 slides
EE 457 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink

EE 457 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink

1 EE 457 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink bottling plant Filling the bottle = 3 sec. Placing the cap = 3 sec. Labeling = 3 sec. Would you want Machine 1 = Does all three (9

776 views • 45 slides
Overview General Principles of Pipelining Goal Computer Architecture: Pipelining

Overview General Principles of Pipelining Goal Computer Architecture: Pipelining

Overview General Principles of Pipelining Goal Computer Architecture: Pipelining Difficulties Creating a Pipelined Y86-64 Processor CSci 2021: Machine Architecture and Organization Rearranging SEQ March 25th-27th, 2020 Inserting

558 views • 6 slides
Power-Optimal Pipelining in Deep Submicron Technology Seongmoo Heo and Krste Asanovi Computer

Power-Optimal Pipelining in Deep Submicron Technology Seongmoo Heo and Krste Asanovi Computer

ISLPED 2004 8/10/2004 Power-Optimal Pipelining in Deep Submicron Technology Seongmoo Heo and Krste Asanovi Computer Architecture Group, MIT CSAIL Traditional Pipelining Goal: Maximum performance Vdd Clk-Q Setup Propagation Delay Clk

615 views • 27 slides
CIS 371 Computer Organization and Design Unit 5: Pipelining Based on slides by Prof. Amir Roth

CIS 371 Computer Organization and Design Unit 5: Pipelining Based on slides by Prof. Amir Roth

CIS 371 Computer Organization and Design Unit 5: Pipelining Based on slides by Prof. Amir Roth &amp; Prof. Milo Martin CIS 371: Comp. Org. | Prof. Milo Martin | Pipelining 1 This Unit: Pipelining Processor performance App App App

1.45k views • 109 slides
Pipelining is Hazardous! Hazards are situations where pipelining does not work as elegantly as

Pipelining is Hazardous! Hazards are situations where pipelining does not work as elegantly as

Pipelining is Hazardous! Hazards are situations where pipelining does not work as elegantly as we would like Three kinds Structural hazards -- we have run out of a hardware resource. Data hazards -- an input is not available on

356 views • 22 slides
Appendix A Appendix A Pipelining: Basic and Intermediate Concepts p 1 Overview Basics of

Appendix A Appendix A Pipelining: Basic and Intermediate Concepts p 1 Overview Basics of

Appendix A Appendix A Pipelining: Basic and Intermediate Concepts p 1 Overview Basics of Pipelining B i f Pi li i Pipeline Hazards Pipeline Implementation Pipelining + Exceptions Pipelining + Exceptions Pipeline

1.39k views • 80 slides
Chapter 5 Managing Process Constraints Theory of Constraints Managing Bottlenecks

Chapter 5 Managing Process Constraints Theory of Constraints Managing Bottlenecks

Chapter 5 Managing Process Constraints Theory of Constraints Managing Bottlenecks Assembly Line Balancing What is a Constraint? Constraint: Any factor that limits the performance of a system and restricts its output.

180 views • 14 slides
CS4617 Computer Architecture Lecture 4: Memory Hierarchy 2 Dr J Vaughan September 17, 2014 1/25

CS4617 Computer Architecture Lecture 4: Memory Hierarchy 2 Dr J Vaughan September 17, 2014 1/25

CS4617 Computer Architecture Lecture 4: Memory Hierarchy 2 Dr J Vaughan September 17, 2014 1/25 Write stall Occurs when processor must wait for writes to complete during write-through Write stalls can be reduced by using a write buffer

479 views • 25 slides
CSEE 3827: Fundamentals of Computer Systems, Spring 2011 8. Processor Performance Prof. Martha

CSEE 3827: Fundamentals of Computer Systems, Spring 2011 8. Processor Performance Prof. Martha

CSEE 3827: Fundamentals of Computer Systems, Spring 2011 8. Processor Performance Prof. Martha Kim (martha@cs.columbia.edu) Web: http://www.cs.columbia.edu/~martha/courses/3827/sp11/ Outline (H&amp;H 7.1) Performance Analysis 2

278 views • 16 slides
Computer Systems Lecture 14 Performance Measures CS 230 - Spring 2020 3-1 CPU Clocking

Computer Systems Lecture 14 Performance Measures CS 230 - Spring 2020 3-1 CPU Clocking

CS 230 Introduction to Computers and Computer Systems Lecture 14 Performance Measures CS 230 - Spring 2020 3-1 CPU Clocking Clock period also called cycle time duration of a clock cycle in units of time SI units of time

2.54k views • 38 slides
CSSE232 Computer Architecture Performance Class status

CSSE232 Computer Architecture Performance Class status

CSSE232 Computer Architecture Performance Class status Reading for today: Sec=ons 1.4-1.9 Lab 2 due soon Class status What should you

641 views • 17 slides
Technology Insertion/Infusion CALCE Electronic Products and Systems Center University of Maryland

Technology Insertion/Infusion CALCE Electronic Products and Systems Center University of Maryland

Technology Insertion/Infusion CALCE Electronic Products and Systems Center University of Maryland Obsolescence/Technology Insertion Design Refreshes Rarely will a design refresh just replace an obsolete part. Usually, if a design refresh is to

380 views • 15 slides
1 CPI (cycles per instruction) CPI (cycles per instruction) Parallelism to save time

1 CPI (cycles per instruction) CPI (cycles per instruction) Parallelism to save time

Processor Execution time Processor Execution time Processor Processor Clock Cycles Instructio n Count Cycles per Instructio n = Performance and Performance and CPU Time Instructio n Count CPI Clock period =

472 views • 4 slides

More recommend