Related Work jTLM, Tasks with Duration sc-during Conclusion Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach Matthieu Moy Grenoble University / Verimag France DATE, March 19 th 2013 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 1 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Modern Systems-on-a-Chip DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 2 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Modern Systems-on-a-Chip Software Hardware DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 2 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Transaction-Level Modeling (Fast) simulation essential in the design-flow ◮ To write/debug software ◮ To validate architectural choices ◮ As reference for hardware verification DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 3 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Transaction-Level Modeling (Fast) simulation essential in the design-flow ◮ To write/debug software ◮ To validate architectural choices ◮ As reference for hardware verification Transaction-Level Modeling (TLM): ◮ High level of abstraction ◮ Suitable for DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 3 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Transaction-Level Modeling (Fast) simulation essential in the design-flow ◮ To write/debug software ◮ To validate architectural choices ◮ As reference for hardware verification Transaction-Level Modeling (TLM): ◮ High level of abstraction ◮ Suitable for Industry Standard = SystemC/TLM DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 3 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Transaction-Level Modeling (Fast) simulation essential in the design-flow ◮ To write/debug software ◮ To validate architectural choices ◮ As reference for hardware verification Transaction-Level Modeling (TLM): ◮ High level of abstraction ◮ Suitable for Industry Standard = SystemC/TLM Issue: SystemC has co-routine semantics ⇒ hard to exploit host parallelism. DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 3 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Outline Existing Parallelization Approaches 1 jTLM, Tasks with Duration 2 sc-during: duration in SystemC 3 Conclusion 4 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 3 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Issues and Solutions for Parallelization Preserve SystemC scheduling semantics 1 Avoid introducing data-races (e.g. i++ on shared variable) 2 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 4 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Issues and Solutions for Parallelization Preserve SystemC scheduling semantics 1 (a) Parallelization within instant/ δ -cycle (b) Optimistic approaches: require specific coding style Avoid introducing data-races (e.g. i++ on shared variable) 2 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 4 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Issues and Solutions for Parallelization Preserve SystemC scheduling semantics 1 (a) Parallelization within instant/ δ -cycle (b) Optimistic approaches: require specific coding style Avoid introducing data-races (e.g. i++ on shared variable) 2 (c) Assume no shared variables (d) Semantics-preserving: don’t run two processes accessing the same variables DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 4 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Issues and Solutions for Parallelization Preserve SystemC scheduling semantics 1 (a) Parallelization within instant/ δ -cycle (b) Optimistic approaches: require specific coding style Avoid introducing data-races (e.g. i++ on shared variable) 2 (c) Assume no shared variables (d) Semantics-preserving: don’t run two processes accessing the same variables Most approaches work for RTL/cycle-accurate: ◮ Clocks ⇒ many processes executing at the same time (a) ◮ sc_signal ⇒ avoids shared variables (c) DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 4 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Issues and Solutions for Parallelization Preserve SystemC scheduling semantics 1 (a) Parallelization within instant/ δ -cycle (b) Optimistic approaches: require specific coding style Avoid introducing data-races (e.g. i++ on shared variable) 2 (c) Assume no shared variables (d) Semantics-preserving: don’t run two processes accessing the same variables Most approaches work for RTL/cycle-accurate: ◮ Clocks ⇒ many processes executing at the same time (a) ◮ sc_signal ⇒ avoids shared variables (c) Problems with loosely timed TLM: ◮ Loose timing ⇒ few processes runnable at the same time (a) ◮ Communication using function calls ⇒ many shared variables (c) ◮ Few wait statements ⇒ 1 SystemC transition touches many variables (d) DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 4 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Our Approach: SC - DURING Goals: ◮ Efficient for loosely timed SystemC/TLM ◮ Existing code should continue working ◮ Work with any SystemC implementation Principle: ◮ Library (adds constructs, feel free not to use them) ◮ Notion of duration Source of inspiration: jTLM (Java simulator) DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 5 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Outline Existing Parallelization Approaches 1 jTLM, Tasks with Duration 2 sc-during: duration in SystemC 3 Conclusion 4 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 5 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM SystemC A B P jTLM Q DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM Process A: // computation SystemC A f(); // time taken by f B wait(20, SC_NS); P jTLM Q DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); P jTLM Q DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: awaitTime g(); P jTLM awaitTime(20); Q DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: awaitTime g(); h() P jTLM awaitTime(20); consumesTime(15) { Q h(); } DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion (Simulated) Time in SystemC and jTLM f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: awaitTime g(); h() P jTLM awaitTime(20); consumesTime(15) { Q i() j() h(); } DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 6 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Execution of consumesTime(T) Fast computation Slow computation Simulated Computation Task Wall-clock time Task Wall-clock time time finishes ends finishes blocked Rest of the platform drives time Task starts Task starts 0 10 20 30 40 0 10 20 30 40 Simulated time Simulated time idle DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 7 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel P3 P4 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 8 / 22 >
Related Work jTLM, Tasks with Duration sc-during Conclusion Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel P3 Non-simultaneous tasks don’t P4 DATE, March 19 th 2013 Matthieu Moy (Verimag) Parallel Programming with SystemC < 8 / 22 >
Recommend
More recommend
