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Simulating Timed UML2 Sequence Diagrams with Timed CSP M Roggenbach (Swansea, Wales, UK) Alexander Knapp, Liam OReilly, and Holger Schlingloff September 2013 What is the added value? 2 What is the added value? Timed UML2 Sequence Diagram

SLIDE 1

Simulating Timed UML2 Sequence Diagrams with Timed CSP

M Roggenbach (Swansea, Wales, UK)

Alexander Knapp, Liam O’Reilly, and Holger Schlingloff

September 2013

SLIDE 2

What is the added value? 2

What is the added value?

Timed UML2 Sequence Diagram (Ventricular Assist Device) Captures the set of “possible timed system behaviours”. Our aim: early system validation by simulation.

M Roggenbach: Simulating; September 2013

SLIDE 3

This is a “first ideas” talk 3

This is a “first ideas” talk

Here:

Timed Sequence Diagrams.
Simulation with Timed CSP Simulator.

In the long run:

Several Timed UML2 diagrams.
Simulation / Model checking with UPPAAL, PAT, FDR2,

Timed CSP Simulator, . . . to check if the various viewpoints “fit” together.

M Roggenbach: Simulating; September 2013

SLIDE 4

Semantics

SLIDE 5

Semantics via Timed Automata 5

Semantics via Timed Automata

Extends semantics of untimed sequence diagrams via

untimed automata by Knapp & Wuttke in 2007.

One clock per time constraint.
Annotations on the transitions: time guards & clock resets.

s_27 s_28 snd(setPumpParametersAck) s_26 rcv(canSetOtherAckLeft) s_29 rcv(setPumpParametersAck) s_74 s_75 rcv(canSetRateRight) s_71 rcv(canSetRateLeft) s_73 s_13 snd(canSetRateAckLeft) s_76 rcv(canSetRateLeft) snd(canSetRateAckRight) s_72 rcv(canSetRateLeft) s_70 s_67 rcv(canSetRateRight) snd(canSetRateAckRight) s_12 snd(canSetRateAckLeft) rcv(canSetRateRight) s_11 snd(canSetRateAckLeft) s_20 s_21 rcv(canSetOtherParamsLeft) s_36 snd(canSetOtherAckRight) s_22 snd(canSetOtherAckRight) s_35 snd(canSetOtherAckLeft) s_23 snd(canSetOtherAckLeft) s_32 rcv(canSetOtherAckRight) s_24 rcv(canSetOtherAckRight) s_25 snd(setOtherParamsAck) rcv(setOtherParamsAck) s_30 rcv(canSetOtherAckLeft) s_69 rcv(setRateAck) s_66 rcv(canSetRateRight) s_68 snd(setRateAck) s_65 rcv(canSetRateRight) s_39 s_34 rcv(canSetOtherParamsLeft) s_16 snd(canSetRateAckRight) s_38 rcv(setOtherParamsAck) s_33 rcv(canSetOtherParamsLeft) rcv(setRateAck) s_15 snd(canSetRateAckRight) s_37 snd(setOtherParamsAck) rcv(canSetOtherParamsLeft) snd(setRateAck) s_14 snd(canSetRateAckRight) s_64 s_62 snd(canSetOtherParamsRight) s_43 rcv(setRateAck) s_63 snd(canSetOtherAckLeft) s_61 snd(canSetOtherParamsRight) s_42 rcv(setRateAck) s_60 rcv(canSetOtherParamsRight) s_41 rcv(setRateAck) snd(canSetOtherAckLeft) s_40 rcv(setRateAck) s_59 rcv(canSetOtherParamsRight) rcv(setRateAck) s_58 snd(canSetOtherAckRight) s_6 s_7 rcv(setPumpParameters) [c_1 <= 30000] s_8 snd(canSetRateLeft) s_4 s_5 rcv(setStartUpAck) snd(setPumpParameters) snd(canSetRateRight) s_9 rcv(canSetRateLeft) snd(canSetRateRight) s_10 snd(canSetRateAckLeft) s_31 rcv(setOtherParamsAck) snd(canSetOtherAckLeft) snd(setOtherParamsAck) rcv(setOtherParamsAck) snd(setPumpParametersAck) s_2 s_3 rcv(setStartUp) / c_1 = 0; snd(canSetOtherAckRight) snd(setStartUpAck) rcv(canSetOtherParamsLeft) rcv(canSetOtherAckRight) snd(canSetOtherAckLeft) rcv(setOtherParamsAck) s_1 snd(setStartUp) snd(canSetOtherAckLeft) s_49 rcv(setRateAck) s_50 rcv(canSetOtherParamsLeft) s_56 snd(setOtherParamsAck) s_48 rcv(setRateAck) rcv(canSetOtherAckRight) s_57 rcv(canSetOtherParamsLeft) s_44 s_45 snd(canSetOtherParamsLeft) [c_2 >= 100] s_17 rcv(setRateAck) rcv(canSetOtherParamsLeft) s_46 snd(canSetOtherParamsRight) s_18 rcv(setRateAck) rcv(canSetOtherParamsLeft) s_47 rcv(canSetOtherParamsRight) s_19 rcv(setRateAck) rcv(setRateAck) snd(canSetOtherAckRight) rcv(canSetOtherParamsLeft) rcv(canSetOtherParamsRight) snd(canSetOtherAckLeft) rcv(canSetOtherParamsRight) snd(canSetOtherParamsRight) snd(canSetOtherAckLeft) snd(canSetOtherParamsRight) rcv(setRateAck) snd(canSetOtherAckLeft) snd(canSetOtherAckRight) rcv(canSetOtherParamsRight) rcv(canSetOtherParamsLeft) snd(canSetOtherParamsLeft) [c_2 >= 100] rcv(canSetOtherParamsLeft) snd(canSetOtherParamsRight) rcv(canSetRateAckRight) / c_2 = 0; rcv(setRateAck) rcv(canSetRateAckRight) / c_2 = 0; snd(setRateAck) rcv(setRateAck) s_55 snd(setOtherParamsAck) s_51 snd(canSetOtherAckLeft) rcv(canSetRateAckLeft) rcv(canSetRateAckLeft) snd(canSetRateAckRight) rcv(canSetRateAckLeft) rcv(canSetRateRight) snd(canSetRateRight) rcv(setRateAck) rcv(canSetOtherAckRight) snd(canSetOtherAckLeft) rcv(setRateAck) rcv(canSetOtherAckRight) rcv(setRateAck) s_52 snd(canSetOtherAckLeft) rcv(setRateAck) rcv(canSetOtherParamsLeft) s_53 rcv(setRateAck) s_54 snd(setPumpParametersAck) rcv(setRateAck) rcv(setRateAck) snd(setOtherParamsAck) rcv(setRateAck) rcv(canSetOtherAckLeft)

M Roggenbach: Simulating; September 2013

SLIDE 6

Encoding Timed Automata within Timed CSP 6

Encoding Timed Automata within Timed CSP

Only a subclass of timed automata needed: simple

encoding possible (less involved than Worrel/Oaknine ’03).

Timed CSP:
closed timed bounds only.
expressions possible rather than constant time bounds only.

tr(S1 → S2{observation obs(m); reset r1; . . . ; reset rn; timing s1 ≥ lb1; . . . ; timing sp ≥ lbp; })

Wait max{lb1 − s1, . . . , lbp − sp, 0} ;
bs.m@x → S2(update(

c, {r1, . . . , rn}, x + max{lb1 − s1, . . . , lbp − sp, 0})) .

M Roggenbach: Simulating; September 2013

SLIDE 7

Tools

SLIDE 8

Current architecture 8

Current architecture

UML Hugo+ TA T-CSP- Converter T-CSP T-CSP Simulator Simulation History Visualiser

M Roggenbach: Simulating; September 2013

SLIDE 9

Demo 9

Demo

M Roggenbach: Simulating; September 2013

SLIDE 10

Conclusion

SLIDE 11

Summary & future work 11

Summary & future work

Validation of Timed UML2 Sequence Diagrams

based on a formal semantics,
through interactive visualisation.

First step towards a simulation and verification framework for timed UML2.

M Roggenbach: Simulating; September 2013