Timed Transition Systems Timed Automata Networks of Timed Automata Equivalence Checking Problems Regions and Region Graph Modelling and Verification Timed Automata: A Formalism for Real-time Systems Labelled transition systems with time Timed automata Timed and untimed bisimilarity Timed and untimed language equivalence Region graph and the reachability problem Networks of timed automata Model checking of timed automata Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph Need for Introducing Time Features Timeouts in protocols: In CCS timeouts were modelled using nondeterminism. Enough to prove that the protocol is safe. Maybe too abstract for certain questions (What is the average time to deliver the message?). Many real-life systems depend on timing: Real-time controllers (production lines, computers in cars, railway crossings). Embedded systems (mobile phones, remote controllers, digital watch). ... Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph Labelled Transition Systems with Time Timed (labelled) transition system (TLTS) a TLTS is a triple ( Proc , Act , { − →| a ∈ Act } ) where Proc is a set of states (or processes), Act = N ∪ R ≥ 0 is a set of actions (consisting of labels and time-elapsing steps), and a for every a ∈ Act , − → ⊆ Proc × Proc is a binary relation on states called the transition relation. We write a → s ′ if a ∈ N and ( s , s ′ ) ∈ a s − − → , and → s ′ if d ∈ R ≥ 0 and ( s , s ′ ) ∈ d d − − → . s Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph How Can One Describe Timed Transition Systems? Syntax Semantics − → unknown entity known entity − → Labelled Transition Systems CCS − → Timed Transition Systems ??? Timed Automata [Alur, Dill’90] Finite-state automata equipped with clocks. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph How Can One Describe Timed Transition Systems? Syntax Semantics − → unknown entity known entity − → Labelled Transition Systems CCS − → Timed Transition Systems ??? Timed Automata [Alur, Dill’90] Finite-state automata equipped with clocks. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph How Can One Describe Timed Transition Systems? Syntax Semantics − → unknown entity known entity − → Labelled Transition Systems CCS − → Timed Transition Systems ??? Timed Automata [Alur, Dill’90] Finite-state automata equipped with clocks. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Motivation Networks of Timed Automata Definition Equivalence Checking Problems Describing Timed Transition Systems Regions and Region Graph How Can One Describe Timed Transition Systems? Syntax Semantics − → unknown entity known entity − → Labelled Transition Systems CCS − → Timed Transition Systems ??? Timed Automata [Alur, Dill’90] Finite-state automata equipped with clocks. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
� � � Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Example: Light switch press ���� ���� ���� ���� � ���� ���� ���� ���� x > 1 . 4 press x ≤ 1 . 4 press x :=0 Light Bright Off press Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Definition of TA: Clock Constraints Let C = { x , y , . . . } be a finite set of clocks. Set B ( C ) of clock constraints over C B ( C ) is defined by the following abstract syntax g , g 1 , g 2 ::= x ∼ n | x − y ∼ n | g 1 ∧ g 2 where x , y ∈ C are clocks, n ∈ N and ∼∈ {≤ , <, = , >, ≥} . Example: x ≤ 3 ∧ y > 0 ∧ y − x = 2 Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Clock Valuation Clock valuation Clock valuation v is a function v : C → R ≥ 0 . Let v be a clock valuation. Then v + d is a clock valuation for any d ∈ R ≥ 0 and it is defined by ( v + d )( x ) = v ( x ) + d for all x ∈ C v [ r ] is a clock valuation for any r ⊆ C and it is defined by � 0 if x ∈ r v [ r ]( x ) = v ( x ) otherwise. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Clock Valuation Clock valuation Clock valuation v is a function v : C → R ≥ 0 . Let v be a clock valuation. Then v + d is a clock valuation for any d ∈ R ≥ 0 and it is defined by ( v + d )( x ) = v ( x ) + d for all x ∈ C v [ r ] is a clock valuation for any r ⊆ C and it is defined by � 0 if x ∈ r v [ r ]( x ) = v ( x ) otherwise. Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Evaluation of Clock Constraints Evaluation of clock constraints ( v | = g ) v | = x < n iff v ( x ) < n v | = x ≤ n iff v ( x ) ≤ n v | = x = n iff v ( x ) = n . . . v | = x − y < n iff v ( x ) − v ( y ) < n v | = x − y ≤ n iff v ( x ) − v ( y ) ≤ n . . . v | = g 1 ∧ g 2 iff v | = g 1 and v | = g 2 Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Syntax of Timed Automata Definition A timed automaton over a set of clocks C and a set of labels N is a tuple ( L , ℓ 0 , E , I ) where L is a finite set of locations ℓ 0 ∈ L is the initial location E ⊆ L × B ( C ) × N × 2 C × L is the set of edges I : L → B ( C ) assigns invariants to locations. g , a , r → ℓ ′ whenever ( ℓ, g , a , r , ℓ ′ ) ∈ E . We usually write ℓ − Timed Automata: A Formalism for Real-time Systems Modelling and Verification
� � Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Example: Hammer start ���� ���� ���� ���� � ���� ���� x :=0 , y :=0 x ≥ 1 hit busy free x :=0 y ≥ 5 done Timed Automata: A Formalism for Real-time Systems Modelling and Verification
Timed Transition Systems Timed Automata Clock Constraints and Valuation Networks of Timed Automata Definition of Timed Automata Equivalence Checking Problems Semantics of Timed Automata Regions and Region Graph Semantics of Timed Automata Let A = ( L , ℓ 0 , E , I ) be a timed automaton. Timed transition system generated by A a T ( A ) = ( Proc , Act , { − →| a ∈ Act } ) where Proc is the collection of states of the form ( ℓ, v ) where ℓ is a location and v a valuation such that v | = I ( ℓ ), Act = N ∪ R ≥ 0 and − → is defined as follows: g , a , r = g and v ′ = v [ r ] a → ( ℓ ′ , v ′ ) if there is ( ℓ → ℓ ′ ) ∈ E s.t. v | ( ℓ, v ) − − → ( ℓ, v + d ) for all d ∈ R ≥ 0 s.t. v | d ( ℓ, v ) − = I ( ℓ ) and v + d | = I ( ℓ ) Timed Automata: A Formalism for Real-time Systems Modelling and Verification
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