Adding Symmetry Reduction to Uppaal M. Hendriks 1 G. Behrmann 2 K.G. - - PowerPoint PPT Presentation

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Adding Symmetry Reduction to Uppaal M. Hendriks 1 G. Behrmann 2 K.G. Larsen 2 P. Niebert 3 F. Vaandrager 1 1 University of Nijmegen, The Netherlands 2 Aalborg University, Denmark 3 Universit e de Provence, France Introduction Motivation

SLIDE 1

Adding Symmetry Reduction to Uppaal

M. Hendriks1
G. Behrmann2

K.G. Larsen2

P. Niebert3
F. Vaandrager1

1University of Nijmegen, The Netherlands 2Aalborg University, Denmark 3Universit´

e de Provence, France

SLIDE 2

Introduction

Motivation

Exploitation of full symmetry can give factorial gain
Full symmetry occurs in many timed systems

⊲ Fischer’s mutex protocol, CSMA/CD protocol (Uppaal benchmarks) ⊲ Dynamic configuration IPv4 addresses (Zhang & Vaandrager) ⊲ Distributed agreement algorithm (Attiya, Dwork, Lynch & Stockmeyer)

SLIDE 3

Introduction

Motivation

Exploitation of full symmetry can give factorial gain
Full symmetry occurs in many timed systems

⊲ Fischer’s mutex protocol, CSMA/CD protocol (Uppaal benchmarks) ⊲ Dynamic configuration IPv4 addresses (Zhang & Vaandrager) ⊲ Distributed agreement algorithm (Attiya, Dwork, Lynch & Stockmeyer)

Approach

Ip & Dill: Better Verification Through Symmetry (1993)

⊲ Scalarsets as fully symmetric data type in description language

Succesfully used in several model checkers

⊲ Murϕ, Spin, Smv

Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 2

SLIDE 4

Outline

(1) Some theory (Ip & Dill, 1993) (2) Implementation

Uppaal language enhancement
Representative computation

(3) Results (4) Conclusions

Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 3

SLIDE 5

Theory (Ip & Dill, 1993)

Syntactical level: system description

P1 P0

B C A B C A

SLIDE 6

Theory (Ip & Dill, 1993)

Syntactical level: system description

P1 P0

B C A B C A

Semantical level: state graph (Q, Q0, ∆)

(A,A) (B,B) (B,A) (C,A) (A,B) (A,C) (C,B) (B,C) (C,C)

SLIDE 7

Theory (Ip & Dill, 1993)

Syntactical level: system description

P1 P0

B C A B C A

Semantical level: state graph (Q, Q0, ∆)

(A,A) (B,B) (B,A) (C,A) (A,B) (A,C) (C,B) (B,C) (C,C)

Detect bijections h : Q → Q in state graph from system description such that ⊲ q ∈ Q0 ⇔ h(q) ∈ Q0 ⊲ (q1, q2) ∈ ∆ ⇔ (h(q1), h(q2)) ∈ ∆

Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 4

SLIDE 8

Theory (2)

Automorphism h on state graph G

(A,A) (B,B) (B,A) (C,A) (A,B) (A,C) (C,B) (B,C) (C,C)

SLIDE 9

Theory (2)

Automorphism h on state graph G

(A,A) (B,B) (B,A) (C,A) (A,B) (A,C) (C,B) (B,C) (C,C)

h induces quotient graph G′

(C,C) (A,A) (C,A) (B,A) (A,B) (C,B) (B,C) (A,C) (B,B)

SLIDE 10

Theory (2)

Automorphism h on state graph G

(A,A) (B,B) (B,A) (C,A) (A,B) (A,C) (C,B) (B,C) (C,C)

h induces quotient graph G′

(C,C) (A,A) (C,A) (B,A) (A,B) (C,B) (B,C) (A,C) (B,B)

Then: q reachable in G ⇐

⇒ [q] reachable in G′

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SLIDE 11

Implementation

(1) Find a set of automorphisms H from the system description

Introduce a symmetric data type, e.g., scalarsets

(2) During state space exploration: [q] =? [q′] (orbit problem)

Use a representative function θ : Q → Q

[q] [q] q q’ q q’

Non canonicalθ Canonical θ Q Q

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SLIDE 12

Language enhancements

Template header: process F (const proc_id pid) Local declarations: clock x;

wait req x<=2 idle cs set==0 x:=0 x:=0, id:=pid, set:=1 set==0 x:=0 x>2, id==pid set:=0

Global declarations: typedef scalarset[3] proc_id; proc_id id; bool set; Process assignments: Procs = forall i in proc_id : F(i); System description: system Procs;

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SLIDE 13

State swap example

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=3 x=4 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=2, set=1

Swap process 0 with process 1

SLIDE 14

State swap example

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=3 x=4 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=2, set=1

Swap process 0 with process 1

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=4 x=3 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=2, set=1

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SLIDE 15

State swap example (2)

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=3 x=4 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=2, set=1

Swap process 1 with process 2

SLIDE 16

State swap example (2)

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=3 x=4 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=2, set=1

Swap process 1 with process 2

x:=0, id:=0, set:=1 x:=0, id:=1, set:=1 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 set:=0 cs wait initial req x<2 x>2, x>2, x>2, id==0 id==1 id==2

x=3 x=4 x=3

set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 set==0 x:=0 x:=0, id:=2, set:=1

id=1, set=1

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SLIDE 17

Representative computation

Idea: “minimize” state using state swaps w.r.t. some total order Problem: symbolic representation of sets of clock valuations (zones) Solution: diagonal property of zones

Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 10

SLIDE 18

Diagonal property

Let x and y be clocks and let Z be a zone (set of clock valuations) x Z y ⇐ ⇒ ∀ν∈Z ν(x) ≤ ν(y) x ≈Z y ⇐ ⇒ ∀ν∈Z ν(x) = ν(y) x ≺Z y ⇐ ⇒ (x Z y ∧ x ≈Z y) Lemma (diagonal property): Consider a symbolic forward state space exploration algorithm. Assume that the clocks are reset to the value 0

nly. For all states (

l, v, Z) stored in the waiting and passed list and for all clocks x and y holds that either x ≺Z y, y ≺Z x, or x ≈Z y.

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SLIDE 19

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0)

SLIDE 20

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset

y x

SLIDE 21

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset

y x y x

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SLIDE 22

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse

y x

SLIDE 23

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse

y x y x

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SLIDE 24

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse (4) Intersection

y x

SLIDE 25

Diagonal property: proof sketch

(1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse (4) Intersection

y x y x

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SLIDE 26

Representative computation (2)

Diagonal property gives a total order on clocks (and on states)

Easily decidable using the DBM representation of zones

State swaps implement transpositions of scalarset elements

All permutations of scalarset elements can be obtained

Representative computation by minimization of state

“Bubble sort” the state with state swaps w.r.t. the total order
Canonical under certain assumptions that involve the discrete

part of the state

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SLIDE 27

Results

0.01 0.1 1 10 100 1000 10000 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 Time [s] Memory [MB] Processes Time Memory Time (prototype) Memory (prototype)

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SLIDE 28

Conclusions

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