Adding Symmetry Reduction to Uppaal M. Hendriks 1 G. Behrmann 2 K.G. - PowerPoint PPT Presentation

Adding Symmetry Reduction to Uppaal M. Hendriks 1 G. Behrmann 2 K.G. Larsen 2 P. Niebert 3 F. Vaandrager 1 1 University of Nijmegen, The Netherlands 2 Aalborg University, Denmark 3 Universit´ e de Provence, France

Introduction Motivation • Exploitation of full symmetry can give factorial gain • Full symmetry occurs in many timed systems ⊲ Fischer’s mutex protocol, CSMA/CD protocol ( Uppaal benchmarks) ⊲ Dynamic configuration IPv4 addresses (Zhang & Vaandrager) ⊲ Distributed agreement algorithm (Attiya, Dwork, Lynch & Stockmeyer)

Introduction Motivation • Exploitation of full symmetry can give factorial gain • Full symmetry occurs in many timed systems ⊲ Fischer’s mutex protocol, CSMA/CD protocol ( Uppaal benchmarks) ⊲ Dynamic configuration IPv4 addresses (Zhang & Vaandrager) ⊲ Distributed agreement algorithm (Attiya, Dwork, Lynch & Stockmeyer) Approach • Ip & Dill: Better Verification Through Symmetry (1993) ⊲ Scalarsets as fully symmetric data type in description language • Succesfully used in several model checkers ⊲ Mur ϕ , Spin , Smv Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 2

Outline (1) Some theory (Ip & Dill, 1993) (2) Implementation • Uppaal language enhancement • Representative computation (3) Results (4) Conclusions Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 3

Theory (Ip & Dill, 1993) Syntactical level: system description P0 P1 A A B B C C

Theory (Ip & Dill, 1993) Syntactical level: system Semantical level: state graph description ( Q, Q 0 , ∆) P0 P1 (A,A) A A (B,A) (A,B) B B (C,A) (B,B) (A,C) (C,B) (B,C) C C (C,C)

Theory (Ip & Dill, 1993) Syntactical level: system Semantical level: state graph description ( Q, Q 0 , ∆) P0 P1 (A,A) A A (B,A) (A,B) B B (C,A) (B,B) (A,C) (C,B) (B,C) C C (C,C) Detect bijections h : Q → Q in state graph from system description such that ⊲ q ∈ Q 0 ⇔ h ( q ) ∈ Q 0 ⊲ ( q 1 , q 2 ) ∈ ∆ ( h ( q 1 ) , h ( q 2 )) ∈ ∆ ⇔ Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 4

Theory (2) Automorphism h on state graph G (A,A) (B,A) (A,B) (C,A) (B,B) (A,C) (C,B) (B,C) (C,C)

Theory (2) Automorphism h on state graph G h induces quotient graph G ′ (A,A) (A,A) (B,A) (A,B) (B,A) (A,B) (C,A) (B,B) (A,C) (C,A) (A,C) (B,B) (C,B) (B,C) (C,B) (B,C) (C,C) (C,C)

Theory (2) Automorphism h on state graph G h induces quotient graph G ′ (A,A) (A,A) (B,A) (A,B) (B,A) (A,B) (C,A) (B,B) (A,C) (C,A) (A,C) (B,B) (C,B) (B,C) (C,B) (B,C) (C,C) (C,C) Then: q reachable in G ⇐ ⇒ [ q ] reachable in G ′ Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 5

Implementation (1) Find a set of automorphisms H from the system description • Introduce a symmetric data type, e.g., scalarsets (2) During state space exploration: [ q ] = ? [ q ′ ] (orbit problem) • Use a representative function θ : Q → Q Q Q [q] [q] q q q’ q’ Canonical θ Non canonical θ Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 6

Language enhancements set==0 req idle x:=0 x<=2 Template header: process F (const proc_id pid) x:=0, set==0 set:=0 x:=0 id:=pid, Local declarations: set:=1 clock x; x>2, cs wait id==pid Global declarations: System description: typedef scalarset[3] proc_id; system Procs; proc_id id ; bool set; Process assignments: Procs = forall i in proc_id : F(i); Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 7

State swap example id=2, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=4 x=3 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, set:=0 x:=0 set:=0 x:=0 set:=0 x:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Swap process 0 with process 1

State swap example id=2, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=4 x=3 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, set:=0 x:=0 set:=0 x:=0 set:=0 x:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Swap process 0 with process 1 id=2, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=3 x=4 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, set:=0 x:=0 set:=0 x:=0 set:=0 x:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 8

State swap example (2) id=2, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=4 x=3 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, x:=0 x:=0 x:=0 set:=0 set:=0 set:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Swap process 1 with process 2

State swap example (2) id=2, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=4 x=3 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, x:=0 x:=0 x:=0 set:=0 set:=0 set:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Swap process 1 with process 2 id=1, set=1 set==0 set==0 set==0 initial req initial req initial req x:=0 x:=0 x:=0 x<2 x<2 x<2 x=4 x=3 x=3 x:=0, x:=0, x:=0, set==0 set==0 set==0 id:=1, id:=2, id:=0, set:=0 x:=0 set:=0 x:=0 set:=0 x:=0 set:=1 set:=1 set:=1 x>2, x>2, x>2, id==0 id==1 id==2 cs wait cs wait cs wait Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 9

Representative computation Idea: “minimize” state using state swaps w.r.t. some total order Problem: symbolic representation of sets of clock valuations (zones) Solution: diagonal property of zones Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 10

Diagonal property Let x and y be clocks and let Z be a zone (set of clock valuations) ⇐ ⇒ ∀ ν ∈ Z ν ( x ) ≤ ν ( y ) x � Z y ∀ ν ∈ Z ν ( x ) = ν ( y ) x ≈ Z y ⇐ ⇒ ( x � Z y ∧ x �≈ Z y ) x ≺ Z y ⇐ ⇒ Lemma (diagonal property) : Consider a symbolic forward state space exploration algorithm. Assume that the clocks are reset to the value 0 only. For all states ( � l, v, Z ) stored in the waiting and passed list and for all clocks x and y holds that either x ≺ Z y , y ≺ Z x , or x ≈ Z y . Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 11

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0)

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset y 0 0 x

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset y y 0 0 0 0 x x Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 12

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse y 0 0 x

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse y y 0 0 0 0 x x Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 13

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse (4) Intersection y 0 0 x

Diagonal property: proof sketch (1) Initial zone satisfies diagonal property (all clocks equal 0) (2) Clock reset (3) Time elapse (4) Intersection y y 0 0 0 0 x x Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 14

Representative computation (2) Diagonal property gives a total order on clocks (and on states) • Easily decidable using the DBM representation of zones State swaps implement transpositions of scalarset elements • All permutations of scalarset elements can be obtained Representative computation by minimization of state • “Bubble sort” the state with state swaps w.r.t. the total order • Canonical under certain assumptions that involve the discrete part of the state Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 15

Results 10000 1000 1000 100 100 Memory [MB] Time [s] 10 1 10 0.1 Time Memory Time (prototype) Memory (prototype) 0.01 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Processes Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 16

Conclusions Adding Symmetry Reduction to Uppaal – FORMATS 2003, September 6-7 2003, Marseille, France 17