P ART 1: O FF -D ETECTOR E LECTRONICS ECAL T ASKS & - PowerPoint PPT Presentation

Les Journées CMS-FRANCE S ELECTIVE R EAD - OUT P ROCESSOR J.-L. Faure, O. Gachelin, P . Gras, I. Mandjavidze, M. Mur CEA Saclay, 91191 Gif-sur-Yvette CEDEX, France Irakli.Mandjavidze@cea.fr O UTLINE O FF -D ETECTOR E LECTRONICS S ELECTIVE R EAD - OUT P ROCESSOR I MPLEMENTATION STUDIES D ISCUSSION A PPENDIXES LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE P ART 1: O FF -D ETECTOR E LECTRONICS → ECAL → T ASKS & ORGANIZATION → A REA & PERIMETER Irakli.Mandjavidze@cea.fr 2 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE T HE CMS E LECTRO M AGNETIC C ALORIMETER • Frontend Electronics Half Barrel → 76832 crystals - electronic channels → 10 samples @ 40 MHz bunch crossing frequency 30600 Channels • Level 1 Trigger 1224 TTs 1224 RUs = → Crystals form L1 trigger primitives: trigger towers → 4032 trigger towers EndCap • Readout → 4 partitions: 2 EndCaps and 2 Half Barrels 7816 Channels → 5 x 5 = 25 crystals form a readout unit 792 TTs 312 RUs → 3072 readout units = (see appendixes for segmentation) Irakli.Mandjavidze@cea.fr 3 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE ECAL O FF -D ETECTOR E LECTRONICS : T ASKS AND O RGANISATION • Control → Interface to Time, Trigger and Control (TTC) system of LHC → Interface to Trigger Control and Trigger Throttling Systems of CMS → Configuration and control of frontends → 54 CCSs (Clock and Control System boards, CERN) • Level 1 Trigger → Receive trigger data from frontends → Form trigger primitives i.e. trigger towers → Transfer trigger tower data to L1 trigger → 108 TCCs (Trigger Concentrator Cards, LLR) • Readout → Receive L1 accepted event data from frontends → Extract relevant calorimeter data according to some selection criteria → Transfer selected data to High Level Triggers and DAQ system → 54 DCCs (Data Concentrator Cards, LIP) + SRP (Selective Readout Processor, Saclay) Irakli.Mandjavidze@cea.fr 4 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE CMS ECAL O FF -D ETECTOR E LECTRONICS : A REA AND P ERIMETER ECAL frontends Clock & control Trigger data Trigger tower All event data L1 Accept TTs generators Level 1 trigger 108 TCCs Clock & Control System LHC Time, TT energies 54 CCSs trigger & control TT classification Readout buffers flags 54 DCCs CMS trigger Selective Readout Selective control Processor readout & throttle SRP flags Selected event data High level triggers & DAQ • 20 VME crates in underground service cavern (see appendixes) Irakli.Mandjavidze@cea.fr 5 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE P ART 2: S ELECTIVE R EAD - OUT P ROCESSOR → M OTIVATION AND G OALS → S ELECTIVE R EAD - OUT A LGORITHMS → F UNCTIONAL D ESCRIPTION Irakli.Mandjavidze@cea.fr 6 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE M OTIVATION AND G OALS • CMS DAQ capabilities → Total event size: 1 Mbyte → Allowed average ECAL event size: 100 Kbyte → Data throughput: ~100 Gbyte/s • Raw data volume of ECAL per event: 1.5 Mbyte → ECAL raw event size exceeds total CMS event size → At 100 kBq L1 Trigger rate ECAL data bandwidth of 150 Gbyte/s > DAQ throughput Reduction factor of almost 20 is necessary • Crystal-by-crystal zero suppression : non-linearity and degraded energy resolution • Selective readout: → Define zones of interest on event-by-event basis → Read full precision data from channels within these zones of interest → Zero suppress the rest of channels Irakli.Mandjavidze@cea.fr 7 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE A T YPE OF S ELECTIVE R EAD - OUT A LGORITHMS • Considered classification of Trigger Towers N N N N N N N N N N E T High N C N High High N N E T N N N N N E T Low Low Low N N N N N Center Neighbours Single Suppressed • Applied read-out algorithms Scheme A Scheme B High Threshold (GeV) 2.0 5.0 Low Threshold (GeV) 0.6 2.5 ZS (0 σ ) Centre All Data ZS (0 σ ) in 3x3 Neighbour All Data in 3x3 or 5x5 Action ZS (0 σ ) Single All Data ZS (3.5 σ ) Suppressed No data • Possibility to achieve necessary data reduction factor - shown (see appendixes) → Note: ECAL is always entirely read with coarse granularity data ( i.e. energy deposited in TTs) Irakli.Mandjavidze@cea.fr 8 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE F UNCTIONAL D ESCRIPTION 40 MHz Level 1 TTs Trigger Data 108 TCCs ECAL front-ends trigger Level 1 Accept 100 kBq All event data 54 DCCs TT classification flags 3 bit / TT 256-deep pipeline 6.4 µ s delay Selective Readout Selective readout flags Processor: SRP 3 bit / flag Selected event data High Level Triggers & DAQ • 108 input links from TCCs • 100 kBq asynchronous operation • 54 output links to DCCs • Processing latency budget ~3-5 µ s • 1.6 Gbit/s links → VME cards of custom FPGA based hardware Irakli.Mandjavidze@cea.fr 9 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE P ART 2: A RCHITECTURE → A DOPTED ARCHITECTURE → SRP I NTERFACES → T ARGETED LAYOUT OF SRP BOARDS → SRP TESTBED Irakli.Mandjavidze@cea.fr 10 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE A DOPTED A RCHITECTURE • Single 6U VME64x Crate • 12 Algorithm Boards (AB) → following 4 ECAL partitions → 3 AB per partition Only one custom board to develop and maintain • Crate Controller (CC) and Boundary Scan (BS) controller → “Standard ECAL” Left Endcap Left 1/2 Barrel Right 1/2 Barrel Right Endcap C B A A A A A A A A A A A A C S B B B B B B B B B B B B Irakli.Mandjavidze@cea.fr 11 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE M APPING OF TCC S , DCC S AND AB S • EndCap: 40 o ϕ sectors with 1 DCC and 4 TCCs • Half Barrel: 17 η x 20 o ϕ Super Modules with 1 DCC and 1 TCC EndCap Half Barrel 18 17 φ 10 9 16 11 8 DCCs in EndCap 15 12 7 14 13 13 6 12 TCCs in EndCap 11 φ 14 5 10 9 DCCs and TCCs 8 15 4 in Barrel 7 6 16 3 5 4 17 2 ABs 3 18 1 2 η 1 η 28 18 17 1 9 DCCs, 36 TCCs, 3 ABs 18 DCCs, 18 TCCs, 3 ABs 3 DCCs & 12 TCCs per AB 6 DCCs & 6 TCCs per AB Irakli.Mandjavidze@cea.fr 12 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE Algorithm Boards • Example of a Barrel AB Left Left Right • Selective read-out algorithm end cap half barrel half barrel ABs ABs ABs → 3 x 3 or 5 x 5 windows slide across η - φ grid η regions 21 18 17 1 1 4 → TTs are classified according their energy 7 (13, 19) → Selective read-out flags are derived accordingly 6 (12, 18) φ sectors of 20 o 5 (11, 17) 4 (10, 26) 3 (9, 15) 2 (8, 14) • The windows cross Algorithm Board boundaries 1 (7, 13) → ABs exchange information about TTs on their edges 18 (6, 12) → Exchanged data is enough for 9x9 sliding windows Irakli.Mandjavidze@cea.fr 13 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE SRP I NTERFACES • With external systems: Trigger Control System and Run Control → CMS standard solutions have been adopted • With other OD Electronics components → Receives TT classification flags from 108 TCCs up to 12 TCCs / AB → Exchange boundary TT classification flags among ABs up to 8 ABs / AB → Sends SR flags to 54 DCCs up to 6 DCCs / AB • Optical communication links have been adopted → allows for high speed connections : 1.6 Gbit/s → alleviates potential problem of distances between ODE components Parallel optic technology for high density design Irakli.Mandjavidze@cea.fr 14 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE SRP C OMMUNICATIONS : TCC - AB - DCC C HANNELS Passive distribution Individual 12-fibre TCC Board module fibres assemblies Algorithm Board Serializer Tx/Rx Up to 12 Rx deserializers DCC Board Up to 12 Tx serializers Deserializer Tx/Rx Optical Transceivers Parallel Optic Small Form factor Pluggable (SFP) 12-Channel MPO with Lucent Connector (LC) Rx and Tx Pairs • SFP and MPO pluggable devices relative freedom in choice of → Manufactures (multi source agreement) → Data rates without changing PCBs Irakli.Mandjavidze@cea.fr 15 / 31 LAPP, Annecy, 11-13 Mai 2004

Selective Read-out Processor Les Journées CMS-FRANCE SRP C OMMUNICATIONS : AB - AB C HANNELS • Passive optical cross-connect for all-to-all AB connectivity Algorithm Board M Up to 12 Rx deserializers Algorithm Board N Up to 12 Tx serializers Irakli.Mandjavidze@cea.fr 16 / 31 LAPP, Annecy, 11-13 Mai 2004