Outline Architectures for CMOS EDC Linear equalizer - - PDF document

8/15/2007 1

Practical Challenges for Electronic Dispersion Electronic Dispersion Compensation in CMOS

Tony Chan Carusone University of Toronto University of Toronto tcc@eecg.utoronto.ca July 23, 2007

Outline

• Architectures for CMOS EDC
• Linear equalizer implementations
• Feedback equalizer implementations
• Towards 40-Gb/s DSP-based EDC
• Conclusions

Practical Challenges for Electronic Dispersion Compensation in CMOS

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• Perform CD compensation optically

Electronic Dispersion Compensation

• PMD compensation must be adaptive to

track changes over milliseconds Fewer taps than EDC for both CD & PMD

Practical Challenges for Electronic Dispersion Compensation in CMOS

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EDC

Optical CD Comp.

• Possibilities

Electronic Dispersion Compensation

–Linear equalization –Decision feedback equalization –MLSE

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EDC

Optical CD Comp.

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IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

Practical Challenges for Electronic Dispersion Compensation in CMOS

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2 2

IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

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2 2

Linear Equalizer Feedback Equalizer

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IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

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2 2

Challenges:

• Inherent delay-bandwidth-gain

tradeoffs

• Timing critical path in the

feedback equalizer

• Extendibility of analog/mixed-

signal approaches to long impulse responses

IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

{

NF NB

}

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2 2

• NF and NB are chosen just large enough to cover

the worst-case (i.e. longest) fiber pulse response

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IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

{

NF NB

}

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2 2

• τB is generally equal to one bit period

since OUT is updated by the clock

IN OUT CLK

DFE Design Parameters

τF τF τB τB IN OUT b2 b1 b0 a2 a1

{

NF NB

}

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2 2

• τF can either be one bit period or a

fraction thereof

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Fractional vs. Baud-Rate Tap-Spacing

• Fractional tap-spacing introduces

correlation between neighboring tap signals ate ing

2 3 4 s

p g This can cause the adaptation engine to become “confused” and to converge slowly, or diverge

• Example:

– 7-tap linear equalizer – Ideal LMS adaptation

0.4 0.5

Baud-Ra Tap-Spac

aud/2

g

2 3 4 2000 4000 6000 8000 10000

• 3
• 2
• 1

1 Time [UI] Tap Weights

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2 4 6 8 0.1 0.2 0.3 Time [UI] Pulse Response

Fractional Tba Tap-Spacin

2000 4000 6000 8000 10000

• 3
• 2
• 1

1 2 Time [UI] Tap Weights

Fractional vs. Baud-Rate Tap-Spacing

Baud-Rate T S i Fractional T S i

• 1

1 2 Eye Pattern

Tap-Spacing

• 1

1 2 Eye Pattern

Tap-Spacing

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0.5 1 1.5 2

• 2

Time [UI] 0.5 1 1.5 2

• 2

Time [UI]

Negligible difference in performance

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Implementation of Linear Equalizer

Feedback Equalizer

Decision Circuit

Linear Equalizer VGA

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3-Tap Traveling Wave Filter

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Passive delay lines consume no power

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3-Tap Traveling Wave Filter

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3-Tap Traveling Wave Filter

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3-Tap Traveling Wave Filter

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LC 2 : spacing Tap = τ πτ π 2 1 : Bandwidth Line Delay

3dB

= = LC f C ∝ per tap gain Maximum

3-Tap Traveling Wave Filter

• Example: Simulated 3-section lumped-LC delay

line designed for 25-ps tap spacing (baud-rate line designed for 25 ps tap spacing (baud rate tap spacing at 40 Gb/s)

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6-Tap Traveling Wave Filter

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LC = τ : spacing Tap πτ π 2 2 : Bandwidth Line Delay

3dB

= = LC f 2 / per tap gain Maximum C ∝

6-Tap Traveling Wave Filter

• Example: Simulated 6-section lumped-LC delay

line designed for the same total delay line designed for the same total delay

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3-Tap Crossover TWF

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3-Tap Crossover TWF

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3-Tap Crossover TWF

Practical Challenges for Electronic Dispersion Compensation in CMOS

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3-Tap Crossover TWF

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3-Tap Crossover TWF

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LC 2 : spacing Tap = τ πτ π 4 2 : Bandwidth Line Delay

3dB

= = LC f C ∝ per tap gain Maximum

Summary

Tap i Delay line b d idth

• Max. gain

t spacing bandwidth per tap 3-tap TWF 6-tap TWF

LC 2 LC LC π 1 2 2 / C ∝ C ∝

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p 3-tap CTWF

LC LC 2 LC π LC π 2 C ∝

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Prototype Implementation

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• 90-nm CMOS process
• 24 mW from 1-V supply

30-Gb/s Equalizer in 90-nm CMOS

Jonathan Sewter, M.A.Sc.

500 μm

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600 μm

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30-Gb/s Equalizer in 90-nm CMOS

Jonathan Sewter, M.A.Sc.

Output Output T-line

500 μm

Input T-line Gain Cells Digital Controls

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600 μm

Input p Preamplifier

Input and output eye diagrams at 20 Gb/s over 12-dB loss channel

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Input and output eye diagrams at 25 Gb/s over 13-dB loss channel

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Input and output eye diagrams at 30 Gb/s over 14-dB loss channel

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3-Tap Crossover TWF

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LC 2 : spacing Tap = τ πτ π 4 2 : Bandwidth Line Delay

3dB

= = LC f C ∝ per tap gain Maximum

3-Tap Crossover TWF

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LC 2 : spacing Tap = τ ??? 6 3 : Bandwidth Line Delay

3dB

πτ π = = LC f C ∝ per tap gain Maximum

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3-Tap Crossover TWF

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3-Tap Crossover TWF

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• Problem: The crossover routing could

introduce skew and crosstalk between paths that must be matched

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Folded-Cascade TWF

• Solution: Alleviate

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Solution: Alleviate crossover routing by introducing an intermediate “folded” transmission line

Folded-Cascade TWF

• Each path through this

network goes through network goes through 5 delay sections and 2 amplifiers

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Folded-Cascade TWF

• Each path through this

network goes through network goes through 5 delay sections and 2 amplifiers

• Each path has a gain
• f a2 (assuming

lossless delay

Practical Challenges for Electronic Dispersion Compensation in CMOS

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y elements)

Folded-Cascade TWF

• Each path through this

network goes through g g 5 delay sections and 2 amplifiers

• Each path has a gain
• f a2 (assuming

lossless delay elements)

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elements)

• There are 9 such paths

Total gain through this tap is 9a2

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Folded-Cascade TWF

• Alternate

interpretation:

Distributed Amp. #2

interpretation: This is a cascade of 2 distributed amplifiers

• Each has a gain of

3a (assuming

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3a (assuming lossless delay elements) Total gain is 9a2

Distributed Amp. #1

3-Tap Folded-Cascade TWF

Tap 1 Tap 2 Tap 3

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• Example: 3-tap FIR filter

Tap 1 Tap 2 Tap 3

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40-Gb/s Equalizer in 0.18-μm CMOS

Jonathan Sewter, M.A.Sc.

• 0.18 μm CMOS

(f = 45 GHz)

Output Output T-line

1 mm

(fT = 45 GHz)

• 3-tap filter
• Fully differential
• Analog control
• f tap weights
• 70 mW from a

Taps Input

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1 mm

1.8 V supply

Input T-line Analog Controls

Input and output eye diagrams at 40 Gb/s over 15-dB loss channel

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Implementation of Feedback Equalizer

Feedback Equalizer

Decision Circuit

Linear Equalizer VGA

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IN OUT CLK

DFE Critical Path

τF τF τB τB IN OUT b2 b1 b0 a2 a1

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2 2

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Infinite Impulse Response Filter

George Ng, M.A.Sc. candidate CLK IN OUT b2 IN OUT b1 b0 a2 a1 τF τF τB τB

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Eliminates timing critical path ⇒ Broadband operation possible in CMOS Possible instability of the filter Complicates the adaptation algorithm

b2 a2

Lookahead DFE

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Lookahead DFE

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• Make a decision assuming the last bit was +1

Lookahead DFE

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• Make a decision assuming the last bit was –1

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Lookahead DFE

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• Choose between the two digitally

Lookahead DFE

Shortened critical path path Parallelism demands more power consumption Clock distribution is a challenge

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challenge

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Lookahead DFE Implementation

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40-Gb/s 1-tap DFE Implementation

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Eliminate clocks from the parallel paths

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40-Gb/s Decision-Feedback Eq.

Adesh Garg, M.A.Sc. (with Prof. S. Voinigescu)

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40-Gb/s Eye Diagrams

Input Eye – 9-ft Electrical Cable Equalized Output Eye

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Jitterpp= 5.11ps; SNR = 9.1 Rise time = 13.67ps; Vpp = 320mV

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Towards 40-Gb/s DSP-based Receivers

Traditional receiver:

Clock CDR Equalizer Clock Data

DSP-based receiver:

Timing Recovery

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A/D

Equalizer Data

• Requires 40-Gsample/sec A/D converter

Ultra High Speed A/D Conversion

Clk Buffer

T/H

Digital Processing Clk In

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15 x 40 Gb/s Pre-Amp & Latch

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CMOS 30-GS/s Track & Hold

Shahriar Shahramian, Ph.D. Candidate (with Prof. S. Voinigescu)

• 0.13-μm CMOS

process process

• 270-mW from

1.8-V supply

• 6.5 ENOB over

7-GHz bandwidth

1 mm

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bandwidth

1 mm

30-GSample/sec Operation

5-GHz input 7-GHz input

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Summary

• Baud-rate tap-spacing in equalizers are

amenable to robust adaptation amenable to robust adaptation

• Techniques to alleviate the inherent delay-

bandwidth-gain tradeoffs in linear equalizers

• Techniques to alleviate the timing

b ttl k i th f db k li

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bottleneck in the feedback equalizer

• Progress towards 40-GSample/sec DSP-

based equalizer