Noise Studies April 4-8 M. Johnson April 2016 1 Testing Crew L. - - PowerPoint PPT Presentation

Noise Studies April 4-8

• M. Johnson

April 2016

1

Testing Crew

• L. Bagby
• S. Chappa
• A. Hahn
• M. Johnson
• B. Kirby
• L. Scott
• T. Shaw
• M. Stancari
• T. K. Warburton

2

Outline

• The presentation is split into 2 parts
• Brian will discuss the following topics
• Adding noise to the low voltage line
• Reducing regulator input voltage to eliminate 11 KHz noise
• Turning off ADC voltages
• Comparison of FFT frequencies to those measured with a spectrum analyzer
• Methods of inducing the high noise state
• I will cover the following topics
• 11 KHz noise based on a hardware modification at Microboone that we did last week
• Short review of previous data on the high noise state
• Spectrum analyzer measurements of the high noise state

3

11 KHz Noise

• We observe an 11 KHz signal that is present across all channels

in all APA’s

• This noise events are correlated in groups that have a common

voltage regulator chip

• FFT’s also show the same phase for wires in a voltage

regulator group

• Microboone sees a very similar effect but in a 20 to 30 KHz

band

• Last week we installed a filter down stream of the warm voltage

regulator which eliminated the microboone noise

Microboone Noise

• Microboone has noise in the 20 to 30 KHz band that is also

associated with voltage regulator groups

• They use the same front end ASIC
• Mother board layout is similar
• Noise is present on the wires
• Frequency width is about 6 times that of the 35 ton
• Microboone has 6 times as many chips per regulator
• All evidence supports the idea that the noise source is identical

5

Microboone Data

• Spectrum analyzer plot looking at the output
• f the intermediate amplifier at feed through

5 at microboone

• Flat noise peak between 20 to 30 KHz
• Flat response is unusual indicating many

different frequencies at the same amplitude

• Noise counts depend on wire length
• U~first 2500,V~2500 to 5000, Y~5000 on
• Noise counts show a marked increase

(spikes in histogram) at the last channel in a MB pair and the starting channel of the next MB pair.

• This corresponds to a group of ASICs

powered by a common voltage regulator

Histogram of noise counts versus wire channel number for µboone

6

Effect of Wire Capacitance

• n µboone Noise Signals
• If the wires for MB pair A or B are at the same

potential, then the inter wire capacitance will have no effect

• However, if the potential for A is different from

B (because of a different phase) then there will be a larger charge stored on A384 than on A383 resulting in a larger noise signal on A384

• Get same effect for B1 so last channel of first

MB pair and first channel of second MB pair should have more noise

• If this interpretation is correct, there must be

noise signal on the wires

• Noise on the wires is likely from a voltage since

noise depends on capacitance (wire length) Simplified schematic showing the last channels

• f mother board pair A and the leading channels
• f mother board B. All capacitor value are assumed

to be equal.

7

Microboone Modification

• Made a proposal to µboone last December to modify a

service board which holds the regulators

• The collaboration agreed to this so I designed a

Chebyshev filter for feed through 5

• Two service boards were modified ao an entire feed

through could be changed

• This was installed last Wed and tests were run over night
• Since this was a kludge, the modified boards were

removed on Thursday

Chebyshev Filter

• Chebyshev filter installed

downstream of the regulator chip (U1 below)

• Cut off is 5 KHz

SPICE model from

• D. Huffman

Chebyshev Filter Microboone Regulator board

9

Filter Results

• Noise reduction before setting ASIC gain and

shaping was ~25db

• After setting gain, the reduction was 12 db or a

factor of 4

• Hardware filter and software filter now give same

results

• The hardware filter removes all the coherent

noise

• Hardware filter has no impact on the signal
• Each ASIC on the mother board a has three 33 µF

and two 0.1 µF bypass capacitors

• While it is possible that it is voltage feed back,

current feed back seems much more likely

10

No Hardware Filter Hardware Filter on Central Region

11

What About the Edge Effect?

• Noise at the edges of the mother

boards appears to actually increase

• Preliminary analysis
• If MB A and B are both oscillating,

sometimes they will have the same voltage and thus no additional noise

• If A is 0, then there will be added

noise whenever B is away from 0 volts so the noise could increase

High Noise Levels

• Lots of information from observations over the last few months
• Ran for 24 hours with cathode off and bias on with no high

noise states

• Ran 24 hours with cathode at 60 KV and bias off with no high

noise states

• High noise state is associated with a current drop on the low

voltage supply for the front end

• Noise has the same frequency over all front end channels

even if only a few show the current drop

High Frequency

• 2 GHz band width so

values below 1 MHz were measured on the turn on slope

• Peaks were still obvious

and matched the ones found in the FFT

• This is conclusive

evidence that the noise signals are present on the wires

Grid signal on APA3 High noise state

14

From Nuno’s Talk Last Week

• There is circumstantial evidence that noise increased with HV drift
• At 60 KV: No noise transitions (according to Alex)
• At 90 KV: Short lived high noise and would recover on its own
• At120 KV: Often in high noise state and only recovered when

power cycling ASICs

• FEMB 9,10, 12-15 were not being used
• Power cycling FEMB-00 was enough to recover low noise
• When started running with only RCE00, 04 and 08 high noise state

became less common

Low Voltage Current Plots From 120 KV Running

• The plot shows that one can have a high noise state with
• nly 2 FEMBs showing a voltage drop and also the direct
• pposite
• This data is also from Nuno.

Spectrum Analyzer Measurements

• Need a method of looking at signals inside the cryostat
• Each APA has a grid plane in front of the wires which is
• nly connected to a bias line
• Nearly ideal antenna into the cryostat
• Only drawback is that it is not a 50 ohm system
• Used 2 spectrum analyzers: 0 to 110 KHz (high

resolution), ~200 KHz to 2 GHz (medium resolution)

17

RCE00 Spectrum

• Low noise state spectrum taken

from APA 7-1 grid

• Two peaks; one at 100 KHz and
• ne at 109 KHz
• Spectrum analyzer resolution is

125 Hz so width of both peaks is less than 200 Hz!

• Consistent with feed back

saturation

• Signal does not change between

high and low noise state

18

FEMB 00 Noise

• 100 KHz noise has been present since

cool down

• It is also present in the high noise state
• Since the bandwidth is so narrow, it is

likely that it has harmonics

• Start up operations such as adding

more ASICs to the readout change the frequencies- often by a large amount

• Last weeks data shows a 60 KHz line

and harmonics.

• Many runs had a 75 KHz or higher

frequency (next slide)

• 19

Data taken last week

High Nose State FFT

Note the large number of evenly spaced lines starting at 75 KHz

20

High Noise Boards

• Not all boards enter the high noise state
• Data below from N Barros shows that different combinations of boards go into the

high noise state

• Spectrum analyzer shows the same frequencies on the grid for all APA’s as seen in

the data

21

External Noise Sources

• Steve Chappa again looked for external noise sources at the 35 ton.
• We found only the 54 KHz from the lights.
• This signal is also seen in the data and in the spectrum analyzer

looking at the grids

• We observed the decay of the spectrum analyzer signal in real time

when the lights were turned off

• Spectrum analyzer signal disappeared when ASIC power was

recycled to start or stop noise (not well documented)

• The variable frequencies observed in the high noise state also

indicate that it is not from an external source

22

Model

• Microboone tests show that there is signal on the wires
• Signal source could be from the supply current or perhaps something with the ASIC
• It is likely that there can also be feed back that is local to a chip.
• This is similar to a microphone placed too close to a speaker which results in a high

pitched squeal

• This would require a very narrow spectral line but this is what we observe in RCE00
• The high noise signal is spread to other boards via capacitive coupling to the close in

cathode

• All grids show the high frequency signals so there has to be some coupling to the

cathode

• Simplest model that has uniform coupling between low regulator current and high

regulator current boards

23

Model Continued

• The large number of uniformly spaced frequencies is due to harmonics of

the narrow spectral line

• The different frequencies depending on configuration are caused by one

ASIC starting up first and the other chips mode locking to this frequency

• Frequency of a single chip depends on the wires (U,V and X)

connected to the ASIC (it is current feed back through the wires)

• Q of a circuit appears to be quite broad so mode locking is easy
• RCE00 has the narrow spectral line both in the low and high power state

so it is often the generator of the noise

• This is confirmed by the observation that turning off the ASICs on

RCE00 usually ends the high noise state.

24

Summary

• All the data support some form of local feed back
• The low frequency (11 KHz) is caused by the voltage regulator

feeding the chips and capacitors on the mother board

• The high frequency (both low and high noise) is likely caused

by a local, non linear feed back for a specific chip

• Feed back through the close cathode and mode locking

causes the entire system to oscillate at fixed frequencies

• The large number of lines in the high noise state is caused by

harmonics of the narrow feed back line

25