METAMOC: Modular Execution Time Analysis Using Model Checking Mads - - PowerPoint PPT Presentation

METAMOC: Modular Execution Time Analysis Using Model Checking

Mads Chr. Olesen <mchro@cs.aau.dk> joint work with Andreas Engelbredt Dalsgaard, Martin Toft, Ren´ e Rydhof Hansen, Kim Guldstrand Larsen

Aalborg University

July 6th 2010

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

(UPPAAL model) Main memory Cache specifications Control Flow Graph (UPPAAL model) Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) executable Annotated value analysis (WALi) Assembly disassemble (objdump, Dissy) (UPPAAL model) Pipeline (Assembly−to−UPPAAL) generate

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph (UPPAAL model) Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) value analysis (WALi) Assembly disassemble (objdump, Dissy) (Assembly−to−UPPAAL) generate executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph (UPPAAL model) Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) value analysis (WALi) Assembly (Assembly−to−UPPAAL) generate executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph (UPPAAL model) Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) value analysis (WALi) (Assembly−to−UPPAAL) generate executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph (UPPAAL model) Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET generate (cache−gen) executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model (UPPAAL model) Caches (UPPAAL models) combine model check (UPPAAL) WCET executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model (UPPAAL model) combine model check (UPPAAL) WCET executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen) Caches (UPPAAL models)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model (UPPAAL model) model check (UPPAAL) WCET executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen) Caches (UPPAAL models) combine

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

model check (UPPAAL) WCET executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen) Caches (UPPAAL models) combine Complete model (UPPAAL model)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

WCET executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen) Caches (UPPAAL models) combine Complete model (UPPAAL model) model check (UPPAAL)

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

executable Annotated (UPPAAL model) Pipeline (UPPAAL model) Main memory Cache specifications disassemble (objdump, Dissy) Assembly (Assembly−to−UPPAAL) generate value analysis (WALi) Control Flow Graph (UPPAAL model) generate (cache−gen) Caches (UPPAAL models) combine Complete model (UPPAAL model) model check (UPPAAL) WCET

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Current Work

Support for pipelines

ARM9TDMI ARM7TDMI ATMEL AVR 8-BIT

Support for instruction/data caches

Automatically generated LRU/FIFO replacement policy

Value analysis for predicting memory accesses

Implemented using Weighted Push-Down Systems Inter-procedural Currently syntactic constant-propagation

Timing anomalies cannot be (consistently) handled

Experiments with caches are with LRU caches, not FIFO as on the real ARM9 3/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

Fetch stage TA Decode stage TA Execute stage TA Memory stage TA Writeback stage TA Process function TAs Data cache TA Instruction cache TA Main memory TA Pipeline Caches Dependency through code Synchronisation

Overview of the ARM9 automata

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

fooCall! fooReturn? done! fetch! main fooCall? fetch! fooReturn! foo

Sketch of the function automata for a process

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

Instruction cache Data cache Main memory ARM9TDMI pipeline Memory stage Writeback stage Execute stage Decode stage Fetch stage ARM920T Caches writeback? Writeback m_done? memory? Memory w r i t e b a c k ! m_done! e_done? execute? Execute m e m

• r

y ! e_done! d_done? decode? Decode e x e c u t e ! d_done! f_done? fetch? d e c

• d

e ! f_done! done? Fetch

ARM9 overview and sketch of pipeline automata

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL Zones

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL Zones

Delay is cheap - large zones

Resilient to different memory wait delays

Many small steps expensive - smaller zones Zones can be collapsed, overapproximation

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Eliminating non-determinism

Since no timing anomalies, cut down on the number of distinct paths as much as possible Pigeonhole optimisations

Iterate loops the maximum number of times Don’t forward jump if path is subset of not jumping

“Executing more code increases the execution time” Can be disabled if timing anomalies present

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Experiments

Evaluation using WCET benchmark programs from M¨ alardalen Real-Time Research Centre

Applicability Performance

Discarded a number of programs

Floating point operations handled by software routines Dynamic jumps Some programs do not compile for our architectures

21 programs for ARM and 19 programs for AVR Manually annotated loop bounds

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Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Experiments

Relative improvement in WCET for ARM9. Analysis times in minutes for AVR and ARM9. 14/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Future Work

Improvements in model checker technology

Our models atypical: more deterministic, longer paths, larger Summarizing long deterministic paths - “short-cuts” Parallel/Distributed model checking Guiding the search - A*

Data sensitivity/flow facts

Track values of registers in model

Timing anomalies

Introduces more non-determinism Improving model checker technology

Schedulability instead of WCET analysis

SARTS project has done this for Java bytecode on the JOP processor 15/17

Thank you for your attention! Questions?

http://metamoc.dk

1

Introduction Overview of METAMOC Current Work

2

Modelling Approach Modelling in METAMOC Model Checking using UPPAAL

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UPPAAL, explained UPPAAL Zones Eliminating non-determinism

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Experiments Experiments

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Future Work Future Work