Memory protection on AVR32 Memory Layout LSE Summer Week 2014 - - PowerPoint PPT Presentation

Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory protection on AVR32

LSE Summer Week 2014 Pierre Surply

EPITA 2016

Jul 19, 2014

Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 1 / 25

Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

AVR32 Architecture

32-bit RISC microprocessor Modified Harvard Up to 15 general-purpose 32-bit registers Instruction length : 16 bits Big-endian Fast interrupts and multiple interrupt priority levels Privileged and unprivileged modes

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

AVR32 AP7

Application Processors 221 DMIPS @ 150 MHz SIMD/DSP Instructions Instruction and Data caches Memory Management Unit Java hardware acceleration

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

NGW100 Development Board

Figure: NGW100

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

AVR32 UC3

Flash Microcontrollers 91 DMIPS @ 66 MHz DSP Instructions Instruction and Data prefetch Memory Protection Unit Embedded Flash/RAM

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

UC3 Development Board

Figure: EVK1100

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Layout

Figure: Memory Map (0x00000000 - 0xFFFFFFFF)

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Layout

Figure: Memory Map (0xC0000000 - 0xDFFFFFFF)

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

External Bus Interface

SDA10 A13 A14 SDWEn SDCKE D14 D15 D8 D9 D10 D11 D12 D13 D6 D7 D0 D1 D2 D3 D4 D5 A11 SDCK A16 A17 CS1n RASn CASn DQM0 DQM1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VCC3 VCC3 R77 4.7k U11 MT48LC16M16A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 VDD1 DQ0 VDDQ1 DQ1 DQ2 VSSQ4 DQ3 DQ4 VDDQ2 DQ5 DQ6 VSSQ3 DQ7 VDD2 DQML WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD3 VSS3 A4 A5 A6 A7 A8 A9 A11 A12 CKE CLK DQMH NC VSS2 DQ8 VDDQ3 DQ9 DQ10 VSSQ2 DQ11 DQ12 VDDQ4 DQ13 DQ14 VSSQ1 DQ15 VSS1 R93 4.7k

Figure: Synchronous DRAM 32MB - 4M x 16 x 4 banks

Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 9 / 25

Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

External Bus Interface

CPU System Bus EBI SDRAM Controller PIO SDRAM AVR32

Figure: EBI Conceptual schematics

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

External Bus Interface

BANK 3 BANK 2 BANK 1 CONTROL LOGIC BANK 0 rows columns

Memory cell

Figure: Generic SDRAM device

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

External Bus Interface

SDRAMC SDRAMC User interface PB PIO SDCK SDCKE SDCS BA[1:0] RAS CAS SDWE NBS[1:0] SDRAMC_A[12:0] D[31:0] AVR32 SDRAM CLK CKE CS BA[1:0] RAS CAS WE NBS[1:0] A[12:0] D[31:0]

Figure: SDRAM Connection

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

External Bus Interface

EBI

D0-D15 A2-A15 RAS CAS SDCK SDCKE SDWE A0/NBS0

2M x 8 SDRAM

D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS1/SDCS D0-D7 D8-D15 A16/BA0 A17/BA1 A18-A23 A10 SDA10 SDA10 A2-A11, A13 NCS0 NCS2 NCS3 A16/BA0 A17/BA1

2M x 8 SDRAM

D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 A2-A11, A13 SDA10 A16/BA0 A17/BA1 NBS0 NBS1 NRD/NOE NWR0/NWE

128K x 8 SRAM 128K x 8 SRAM

D0-D7 D0-D7 A0-A16 A0-A16 A1-A17 A1-A17 CS CS OE WE D0-D7 D8-D15 OE WE NRD/NOE A0/NWR0/NBS0 NRD/NOE NWR1/NBS1 SDWE SDWE

EBI

D0-D15 A2-A15 RAS CAS SDCK SDCKE SDWE A0/NBS0

2M x 8 SDRAM

D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS1/SDCS D0-D7 D8-D15 A16/BA0 A17/BA1 A18-A23 A10 SDA10 SDA10 A2-A11, A13 NCS0 NCS2 NCS3 A16/BA0 A17/BA1

2M x 8 SDRAM

D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 A2-A11, A13 SDA10 A16/BA0 A17/BA1 NBS0 NBS1 NRD/NOE NWR0/NWE

128K x 8 SRAM 128K x 8 SRAM

D0-D7 D0-D7 A0-A16 A0-A16 A1-A17 A1-A17 CS CS OE WE D0-D7 D8-D15 OE WE NRD/NOE A0/NWR0/NBS0 NRD/NOE NWR1/NBS1 SDWE SDWE

Figure: EBI Connections to Memory Devices

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection Unit

AVR32UC CPU pipeline

Instruction memory controller High Speed Bus master

MPU

High Speed Bus High Speed Bus

OCD system

OCD interface Interrupt controller interface

High Speed Bus slave

High Speed Bus Data RAM interface

High Speed Bus master

Power/ Reset control

Reset interface

CPU Local Bus master

CPU Local Bus

Data memory controller

Figure: Overview of the AVR32UC CPU

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection Unit

Allows the user to divide the memory space into different protection regions. Each region is divided into 16 subregions, each of these subregions can have one of two possible sets of access permissions. AVR32 Architecture Document This is a simpler alternative to a full MMU, while at the same time allowing memory protection.

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

MPU Exception Handling

ITLB Protection Violation DTLB Protection Violation ITLB Miss Violation DTLB Miss Violation TLB Multiple Hit Violation

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection Unit

Base Address Size 5 12 31

MPUARn

• 31
• 8

7 6 4 3 2 1 31 31 E 31

MPUCR

• 1

11 6 V 1

MPUCRA / MPUCRB

5

MPUBRA / MPUBRB

• 8

7 6 4 3 2 1 5

MPUAPRA / MPUAPRB

AP0 AP1 AP2 AP3 AP4 AP5 AP6 AP7 3 4 7 8 11 12 15 16 19 20 23 24 27 28

• 31

MPUPSRn

P10 P11 P12 P13 P14 P15 P4 P5 P6 P7 P8 P9 P0 P1 P2 P3 8 7 6 4 3 2 1 5 9 16 15 13 12 11 10 14 C4 C5 C6 C7 C0 C1 C2 C3 B4 B5 B6 B7 B0 B1 B2 B3

Figure: MPU Registers

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

System Registers

__asm__ volatile ("mfsr %0, %1" : "=r" (res) : "i" (addr)); __asm__ volatile ("mtsr %0, %1" : : "i" (addr), "r" (value));

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection

Figure: Basic MPU configuration

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection

Figure: Application MPU configuration I

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection

Figure: Application MPU configuration II

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection

Figure: Application address space

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Memory Protection

Figure: Builtin MPU Configuration

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Conclusion

Not an alternative to a full MMU

Limited number of regions Fixed size regions

FreeRTOS-MPU

vTaskAllocateMPURegions() portSWITCH TO USER MODE() xTaskCreate() -> xTaskCreateRestricted()

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Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion

Contact

Git: git.psurply.com/atucos IRC: Ptishell@irc.rezosup.org Mail: surply@lse.epita.fr Twitter: @Ptishell

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