Memory: Paging Summer 2011 Cornell University 1 Today What is - - PowerPoint PPT Presentation

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Memory: Paging Summer 2011 Cornell University 1 Today What is - - PowerPoint PPT Presentation

CS 4410 Operating Systems Memory: Paging Summer 2011 Cornell University 1 Today What is paging and why do we need it? Paging Address translation scheme Page table Implementation of page table TLB Structure of page


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CS 4410 Operating Systems

Memory: Paging

Summer 2011 Cornell University

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Today

  • What is paging and why do we need it?
  • Paging
  • Address translation scheme
  • Page table
  • Implementation of page table
  • TLB
  • Structure of page table in memory
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Paging

  • Memory management scheme.
  • Noncontiguous physical address space of a

process.

  • The process is allocated physical memory wherever

the latter is available.

  • It avoids external fragmentation.
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Paging

  • Divide physical memory into fixed-sized blocks called

frames (size is power of 2, between 512 bytes and 8,192 bytes)

  • Divide logical memory into blocks of same size called

pages

  • Keep track of all free frames.To run a program of size

n pages, need to find n free frames and load program

  • Set up a page table to translate logical to physical

addresses

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Paging

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Address Translation Scheme

  • Address generated by CPU is divided into:
  • Page number (p) – used as an index into a page table

which contains base address of each page in physical memory

  • Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit

p d m - n n page number page

  • ffset
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Address Translation Scheme

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Address Translation Scheme

0000 a 0001 b 0010 c 0011 d 0100 e 0101 f 0110 g 0111 h 1000 i 1001 j 1010 k 1011 l 1100 m 1101 n 1110

  • 1111

p

logical memory

00 101 01 110 10 001 11 010

page table

00000 00100 i j k l 01000 m n

  • p

01100 10000 10100 a b c d 11000 e f g

physical memory

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Paging

  • User's view: memory is one single space
  • Actual view: the program is scattered

throughout physical memory

  • The OS manages physical memory.
  • Frame table: Availability and owner of every frame
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Hardware Support

  • The OS allocates one page table per process.
  • A pointer to the page table is stored in the PCB.
  • The dispatcher defines the correct hardware

page-table values.

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Implementation of page table

  • Set of dedicated registers.
  • Fast
  • Small
  • In memory
  • Page-table base register (PTBR)
  • Slow
  • Large
  • TLB + memory
  • Translation look-aside buffer
  • Special, small, fast-lookup hardware cache
  • Contains a few of the page-table entries
  • If page_number is in TLB get frame_number out
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Paging Hardware With TLB

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Memory Protection

  • Implemented by associating protection bit with

each frame.

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Shared Pages

  • Shared code
  • One copy of read-only (reentrant) code shared among

processes (i.e., text editors, compilers, window systems).

  • Shared code must appear in same location in the logical

address space of all processes

  • Private code and data
  • Each process keeps a separate copy of the code and data
  • The pages for the private code and data can appear

anywhere in the logical address space

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Structure of the Page Table

  • Hierarchical Paging
  • Hashed Page Tables
  • Inverted Page Tables
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Hierarchical Paging

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Hierarchical Paging

  • Two-Level Paging Example
  • A logical address (on 32-bit machine with 4K page size) is divided into:
  • a page offset of 12 bits
  • a page number of 20 bits
  • Since the page table is paged, the page number is further divided into:
  • a 10-bit page number
  • a 10-bit page offset
  • Thus, a logical address is as follows:

page number page offset p1 p2 d 10 10 12

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Hierarchical Paging

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Hashed Page Tables

  • Common in address spaces > 32 bits
  • The virtual page number is hashed into a page table.

This page table contains a chain of elements hashing to the same location.

  • Virtual page numbers are compared in this chain

searching for a match. If a match is found, the corresponding physical frame is extracted.

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Hashed Page Tables

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Inverted Page Table

  • One entry for each real page of memory.
  • Entry consists of the virtual address of the page stored

in that real memory location, with information about the process that owns that page.

  • Decreases memory needed to store each page table,

but increases time needed to search the table when a page reference occurs.

  • Use hash table to limit the search to one — or at most

a few — page-table entries.

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Inverted Page Table

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Today

  • What is paging and why do we need it?
  • Paging
  • Address translation scheme
  • Page table
  • Implementation of page table
  • TLB
  • Structure of page table in memory