Memory Devices Small: Register file (group of numbered registers) - - PowerPoint PPT Presentation

Memory Devices

Small: Register file (group of numbered registers) Medium: SRAM (Static Random Access Memory) Large: DRAM (Dynamic Random Access Memory) Future?

1

ALU

Processor: Data Path Components

Registers Memory

Instruction Fetch and Decode

1 2 3

SRAM: Static Random Access Memory

SRAM 2M 3 16 Dout[15–0] Address 21 Din[15–0] 16 Chip select Output enable Write enable 16

3

SRAM read port: data out

Large register files are impractical. Big MUX = significant gate delay. Large memories use a shared output line. No central gates/MUX to choose output!

5

Wired ORs

Danger, Will Robinson! (don't try this at home/in the lab, kids)

6

(noninverting) tristate buffers

Control In Out In Control Out Z 1 Z 1 1 1 1

7

(active high)

SRAM cell

8

• ne option

Q D C D Latch Q Enable Data In Clock Data Out

Tristate Buffer

SRAM write port:

latch D C Enable Q D 2-to-4 decoder Write enable Din[1] latch D C Enable Q D Din[1] Dout[1] Dout[0] latch D C Enable Q D 1 latch D C Enable Q D latch D C Enable Q D 2 latch D C Enable Q D latch D C Enable Q D 3 latch D C Enable Q D Address

Write enable Address

Dout[1] Dout[0] Din[1] Din[0] 2-to-4 decoder

1 2 3 Write enable Address select

Din[i]

latch D C Enable Q D

Data out: Data in:

Dout[i]

Organization of a 16 x 4 SRAM

10

4 to 16 decoder 4-bit address data

• ut

(one option)

Selecting location 1101

4 to 16 decoder data

• ut

1101

11

4-bit address

Another organization of a 16 x 4 SRAM

top 2 bits address

Mux Mux Mux Mux

bottom 2 bits address Split-level row/column addressing = physical multidimensional array! (row) (column)

12

2 to 4 decoder

Notice the smaller decoder... how does this affect timing?

Selecting location 0010

top 2 bits address

Mux Mux Mux Mux

bottom 2 bits address (row) (column)

13

2 to 4 decoder Nibbles "striped" across 4 smaller memories.

0010 10 00

2 2 4

Selecting location 1101

top 2 bits address Mux Mux Mux Mux bottom 2 bits address (row) (column)

14

2 to 4 decoder

Nibbles "striped" across 4 smaller memories.

1101 01 11

2 2 4

What value does location 1010 hold?

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Mux Mux Mux Mux

15

2 to 4 decoder

1010

2 2 4

Organization of a 4M x 8 SRAM

12 to 4096 decoder Address [21–10] 4096 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM Mux Dout7 Mux Dout6 Mux Dout5 Mux Dout4 Mux Dout3 Mux Dout2 Mux Dout1 Mux Dout0 1024 Address [9–0]

= 4 MB memory, size of a large cache for modern laptop

In practice, single set of data lines often time-shared for read (out)/write (in).

16

(one option)

Dynamic RAM = DRAM

DRAM stores bit as charge on capacitor:

• 1 transistor accesses stored charge.
• requires periodic refresh = read-write

(dynamic power) SRAM stores bit on pair of inverting gates:

• several transistors
• requires continuous (static) power.

Word line Pass transistor Capacitor Bit line 17

DRAM design

Address[10–0] Row decoder 11-to-2048 2048 2048 array Column latches Mux Dout

Accesses entire row, stores in column latches. Mainly used for refreshing entire row at a time. Accessing other columns in same row again cheaper...? Single set of address lines, time-shared for row address, column address.

18

(one option)

64-bit DRAM

3 to 8 row decoder Mux Column latches

19

3-bit address Data out

Reading bit at address 101011

• 1. Select row

3 to 8 row decoder Mux Column latches

20

3-bit address

101

Data out

Reading bit at address 101011

• 2. Copy row to latches

3 to 8 row decoder Mux Column latches

21

Row is fading!

3-bit address

101

Data out

Reading bit at address 101011

• 3. Refresh row from latches

3 to 8 row decoder Mux Column latches

22

Refresh.

3-bit address

101

Data out

Reading bit at address 101011

• 4. Select column from latches

3 to 8 row decoder Mux

3-bit address

Column latches

23

011

Data out