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M bius Microsystems MEMS and CMOS Approaches to Monolithic Timing - - PowerPoint PPT Presentation

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M bius Microsystems MEMS and CMOS Approaches to Monolithic Timing and Frequency Synthesis University of Utah March 28, 2005 Michael S. McCorquodale, Ph.D. Chief Executive and Technology Officer Mobius Microsystems, Inc. Detroit, MI M. S.

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Microsystems

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  • M. S. McCorquodale

MEMS and CMOS Approaches to Monolithic Timing and Frequency Synthesis

Michael S. McCorquodale, Ph.D. Chief Executive and Technology Officer Mobius Microsystems, Inc. Detroit, MI University of Utah March 28, 2005

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Overview

  • An Overview of Timing and Frequency Synthesis
  • Critical Metrics
  • Entrenched Technologies
  • Emerging MEMS Approaches
  • CMOS Approaches
  • RF Clock Synthesis for the UMICH-WIMS µsystem
  • Mobius’ Clock Synthesis Technology
  • Future Work and Summary of Results
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An Overview of Timing and Frequency Synthesis

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An Overview of Timing and Frequency Synthesis

Timing

Every synchronous semiconductor component requires a clock to operate

Frequency synthesis

RF systems require precision frequency references for carrier frequency synthesis

Bluetooth/LAN USB Print Server

  • USB XTAL clock reference
  • Ethernet XTAL clock reference
  • Processor XTAL clock reference
  • Bluetooth radio XTAL reference (on flip side)
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Frequency Synthesis Approaches

  • The phase, delay, or injection locked “bottom-up” approach

– Resonator (of some type) serves as a frequency reference – Sustaining oscillator provides a low frequency reference signal – PLL/DLL/ILL multiplies frequency by 2-4096x

  • Drawbacks with this approach

– External components (1 resonator + 2 capacitors)

  • Expensive, large, pin interface

– Reference oscillator required

  • Either included in PLL or design required

– PLL dissipates substantial power to multiply frequency

  • Particularly true for large multiplication factors

– Performance degrades as frequency increases

  • For multiplication factor N, noise increases by N2 (to be shown)

– Lock and start-up time can be long (e.g. >10,000 cycles)

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Frequency Synthesis Approaches

  • The free-running “direct” approach

– RC (phase shift), ring, relaxation oscillators – Designed on-chip for the desired frequency – No external components required (monolithic); No reference

  • Drawbacks with this approach

– Very inaccurate: frequency ±20% untrimmed, ±2% trimmed – Very unstable over power supply & temperature variation: ±2% – High jitter – Typically found in 4-bit microcontrollers

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Frequency Synthesis Approaches and Implementations

Free-running fo Discrete Hybrid

µC crystal

Monolithic

clock

Phase-locked Nfref fref ÷N LPF CP PFD

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Critical Metrics

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Summary of Critical Metrics

  • Frequency and time domain metrics

– Short-term frequency stability: Jitter and phase noise – Total frequency accuracy: Drift over process, voltage, temperature (PVT), and aging – Rise/fall times – Duty cycle – Start-up time

  • Environmental conditions

– Sensitivity to microphonics, moisture, etc.

  • Cost

– Fabrication process technology – Production trimming requirements – Packaging requirements

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Short-Term Frequency Stability

)) ( cos( )) ( ( ) ( t t t V t v

  • n

φ ω ε + + =

Noisy Oscillator Output

Timing Jitter

Time domain uncertainty in period

Ideal Period

t v t vn

T1 T2 T3 t1 t2 t3 t4

Phase Noise

Power at frequency offset from fundamental

f fo P f fo P

t V t v

  • ω

cos ) ( =

Ideal Oscillator Output

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Short-Term Frequency Stability

Short-Term Timing Jitter Expressions

  • n-cycle
  • Period (1-cycle)
  • Cycle-to-cycle

) var( ) (

k n k n

t t k J − =

+

J T t t k J

k k k

= = − =

+

) var( ) var( ) (

1 1

) var( ) (

1 k k cc

T T k J − =

+

  • m
  • v

f

  • P

f f S P N

m

) ( + = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

Phase Noise Power Spectral Density (PSD) Power relative to fundamental at offset fm from fo

t t

Ideal Period

v vn

T1 T2 T3 t1 t2 t3 t4

f fo P fo+fm

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Frequency Accuracy and Precision

ref ref actual f

f f f A − =

f f f Pf − =

max

Nominal frequency acc./prec.

  • Accuracy is how close the actual

frequency is to the desired (fref)

  • Precision is how much the maximum

frequency deviates from the mean ( f ), an issue that must be addressed in production

  • Will frequency trimming be required?

If so, what will it cost (test time)

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Frequency Sensitivities or Drift

  • Power supply
  • Temperature
  • Microphonic

DD DD f V

V f f V S

DD

∂ ∂ =

T f f TC f ∂ ∂ = 1

G f f G S f

G

∂ ∂ = All expressions can be determined by analysis

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Long-Term Frequency Stability

Long-term frequency stability

  • A measure of frequency variation over a long period of time
  • Commonly called aging

Short-term instability

t

Long-term instability

∆f f

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Entrenched Technologies

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Entrenched Technologies

  • Quartz

– Piezoelectric bulk acoustic wave (BAW) resonators – ±50 to ±250ppm total accuracy – kHz to 100MHz – Primary applications: frequency and clock synthesis

  • ZnO

– Piezoelectric surface acoustic wave (SAW) resonators – ±100 to ±250ppm total accuracy – 100 to 900MHz – Primary application: IF filters

  • Ceramic

– Ceramic material which is induced to be piezoelectric – ±0.25 to ±5% total accuracy – kHz to 50MHz – Primary application: clock synthesis

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Emerging MEMS Approaches

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Two General Approaches

  • Resonator replacements

– Utilize micromachining to develop integrated mechanical resonators which can replace discrete resonators – Intended to enable the realization of an integrated time/frequency reference

  • Improve VCO performance with enhanced

passive components

– Develop high-Q varactors and inductors in order to realize low phase noise VCOs – Not intended to replace the reference, but related to improving the performance of frequency synthesis blocks (allows Q-factor of reference oscillator to be relaxed)

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Emerging MEMS Approaches

  • Capacitively-coupled microresonators

– Surface micromachined poly-Si structures with capacitive actuation

  • Benefits

– Very high-Q (>10,000) demonstrated

  • Challenges

– High motional resistance (>kΩ) – Nonlinear transduction causes flicker noise upconversion in oscillator circuits – Specialized packaging required – Process not CMOS-compatible – Frequency trimming required – Moderate temperature coefficient – Microphonic sensitivity may be high

Clamped-clamped beam poly-Si microresonator [Nguyen, McCorquodale, et al.] Disk poly-Si microresonator [Nguyen, et al.]

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Emerging MEMS Approaches

  • Piezoelectrically-coupled

microresonators

– ZnO film couples actuation to surface micromachined poly-Si beam – Remainder of device identical to previous microresonator

  • Benefits

– Much lower motional resistance than previous microresonator (~100Ω)

  • Challenges

– Same as remaining challenges for previous microresonators

Tuning Capacitor Handle Layer Oxide Device Layer ZnO Film Sense Electrode Drive Electrode

Piezoelectric microresonator [Ayazi, et al.]

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Emerging MEMS Approaches

  • Piezoelectric film bulk acoustic wave resonators (FBAR)

– Similar to an integrated XTAL, but a film

  • Benefits

– High-Q – Low motional resistance – No specialized packaging required

  • Challenges

– Not CMOS-compatible – Accuracy difficult to control

  • Actually in products
  • Best application: multiple

references/filters within one package

Electrodes Piezoelectric Reflectors Substrate Substrate

Drive Electrode Thin Piezoelectric Film

FBAR [Ruby, et al.]

Sense Electrode

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Emerging MEMS Approaches

  • Passive RF MEMS

– Micromachined varactors and inductors of various topologies

  • Benefits

– Higher Q than planar passive components and thus lower phase noise in VCOs – Often tunable via mechanical actuation – Some devices CMOS-compatible

  • Challenges

– Most devices not CMOS-compatible – Microphonic sensitivity high for large aspect ratio devices – Some devices not practical for high volume production

Micromachined parallel plate varactor [Young, Boser] Micromachined suspended inductor [Yoon]

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CMOS Approaches

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General Approach

  • Construct a reference oscillator at desired

frequency with available CMOS components: resistors, capacitors, transistors, diodes, etc.

  • Use standard and well-known oscillator

topologies

  • Design compensation circuitry for voltage and

temperature drift

  • Trim frequency out of fabrication
  • Best accuracy achieved to date ~±1.5% over PVT
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Phase Shift Oscillator

Basic operation

  • Minimum of three RC pairs to

form 180º phase shift

  • Inverting amplifier creates final

180º phase shift

  • fo dependent on RC component

values

Challenges

  • Poor temperature stability
  • Poor short-term stability
  • Moderate accuracy (trimmed)
  • Moderate Si area

RC

  • 6

= ω

  • A

R C R R C C

Notes

  • Very common in MCUs
  • All discrete Si clock components

utilize phase shift topology

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Relaxation and Ring

Relaxation: Basic operation

Characterized by one equivalent storage element as reference

D m

  • RCC

g 2 = ω

Ring: Basic operation

Odd number of inverters in a ring or an even number with wire inversion

d

  • nt

2 2π ω =

Challenges for both

  • Very inaccurate
  • Poor short-term stability
  • Poor temperature stability

…

1 2 n

M1 M2 C R R

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RF Clock Synthesis for the UMICH-WIMS µsystem

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µsystem Applications

Biomedical Implants

Cochlear Implant Deep Brain Implants µGas Chromatograph

Environmental Sensors

Heavy Metal Sensing

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µsystem Development Requirements

Minimize transmitted data and associated power Minimize form factor and packaging cost, some applications are aqueous Sensor data requires processing only periodically System battery operated and battery EOL voltage ~900mV

Purpose

Low-latency clock frequency switching and fast start-up time Support processing “bursts” from 2kHz to 66MHz AFE captures analog sensor data, ISA supports sufficient instructions for data processing, 64KB

  • n-chip SRAM

Sufficient local data processing and storage Monolithic clock reference Fully encapsulated µsystem Low power digital core, 900mV AFE, low power clock reference Operation voltage from 1.8V to 900mV

Solution System Requirements

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WIMS µsystem Block Diagram

External Memory Memory Management Unit Fetch Decode Execute Register Files Boot ROM 64KB RAM Timer X2 USART X3 SPI X2 Test Int. ADC Int. Loop Cache

Monolithic Clock Synthesizer

PGA

Buffer Buffer

Vin+ Vin- Analog Front End

Σ∆ Σ∆ ADC

By Fadi Gebara and Keith Kraver By Rob Senger, Eric Marsman, Dan Burke, and Matt Guthaus

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Research Goals

  • Develop a clock synthesizer that is:

Difficult Fast (start-up and frequency switching) Very difficult Low-drift over PVT Very difficult Low-jitter Very difficult High-accuracy Difficult Low-Power Difficult Small (Si footprint) Difficult CMOS-compatible (in Si) Difficult Monolithic (no external components)

  • Demonstrate clock synthesizer:

– As an autonomous block – As the sole clock reference for the µsystem

  • Develop any supporting technology
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General Approach

  • Initial Research Thoughts

– Achieving low jitter and acceptable PVT drift requires a harmonic reference (Q >> 1) – Mechanical references are too expensive/complicated to integrate with CMOS – Look at the problem from the RF world: The LC oscillator is a workhorse, but LC sizes at ~66MHz are too large to integrate & are low-Q

  • Thoughts Toward the Developed Approach

– Must free-run and not phase-lock for fast start-up and low-latency switching – Turn the ubiquitous frequency synthesis approach upside-down

  • Start at high fo, square, & translate to more stable low frequency
  • Starting at a high fo limits the LC size and keeps Si area down
  • Investigate use of micromachining to improve Q for LC components

– Develop some electrical frequency trimming approach – PVT compensation

  • First determine overall performance of LC oscillator for clocking
  • Next determine compensation techniques
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The Importance of Frequency Translation

dt dφ ω =

Phase and frequency are related by a linear operator

)) ( cos( ) ( t t V t v

n

  • n

φ ω + =

)) ( cos( ) (

,

t N t N V t v

n

  • mult

n

φ ω + =

Frequency mult./div. results in phase noise mult./div. Using narrowband FM approximation

) log(

2 . / . ,

N P N P N

m m

f

  • div

mult f

  • ±

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

Linear freq. trans. results in quadratic change in noise power

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Relationship with Q-Factor

Nmult for XTAL+ PLL up to 4096 High-Q, but large degradation: Can consider “effective” Q

2 2

8 1 ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛

m

  • fm
  • f

f Q C FkT C N

Leeson Phase Noise Model Q-factor quadratically related to phase noise PSD Frequency Translation Frequency translation also quadratically related to phase noise PSD

) log(

2 . / . ,

N P N P N

m m

f

  • div

mult f

  • ±

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

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Converting Phase Noise to Period Jitter

Two common expressions for converting phase noise to jitter

  • Kundert’s expression is actually just a specialized case of the

expression by Drakhlis (i.e. an estimate)

  • Phase noise is related to jitter by a square root

m

f

  • m

P N f f J ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

3 2

[Kundert] Uses Lorentzian assumption by [Demir]

∫

∞

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

2 2

sin 8 df f P N J

m

f

  • τ

π ω

[Drakhlis] τ = Τ Τ = 1/fo

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Effect of Frequency Translation

Using phase noise conversion expression, determine jitter:

N J/ Nf f P N N J

  • m

f

  • mult

m

= ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

3 2 2

) ( J N N f f P N N J

  • m

f

  • div

m

= ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

3 2 2

) / ( 1

Considering fractional, or ppm, jitter:

6

10 / T J J ppm =

Frequency translation can enhance or degrade jitter

ppm mult ppm

J N N T N J J = =

6 ,

10 / ) / ( /

N J NT J N J

ppm div ppm

/ 10 /

6 ,

= =

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Jppm

Relative Period Jitter (ppm)

J

Period Jitter (s) SSB Phase Noise PSD (dBc/Hz)

fref /N Nfref fref

Output Frequency (Hz)

Frequency Division Frequency Multiplication Reference Oscillator Variable/Metric

Frequency Translation Summary N J /

m

f

  • P

N ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

) log( 20 N P N

m

f

  • +

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ) log( 20 N P N

m

f

  • −

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

J N

N J ppm /

ppm

J N

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Typical Ring-PLL Phase Noise and Jitter (N = 64)

10

1

10

2

10

3

10

4

10

5

10

6

10

7

  • 150
  • 125
  • 100
  • 75
  • 50
  • 25

Offset Frequency (Hz) Phase Noise Spectral Density (dBc/Hz) Bottom-up Reference Oscillator Bottom-up VCO Bottom-up Synthesizer Output ~20log(64)

PLL Loop BW Significant noise at large

  • ffsets

Consider Intel SA-1110

  • Strong-ARM mobile

µP for PDAs

  • 3.6864MHz XTAL
  • 64X Ring-PLL
  • Max fclk = 236MHz
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Typical LC Oscillator Phase Noise and Jitter (N = 16)

10

1

10

2

10

3

10

4

10

5

10

6

10

7

  • 150
  • 125
  • 100
  • 75
  • 50
  • 25

Offset Frequency (Hz) Phase Noise Spectral Density (dBc/Hz) Top-down Reference Oscillator Top-down Synthesizer Output ~20log(16)

Little noise at large

  • ffsets

Consider typical LC-VCO

  • Free-running
  • fo = 3.78GHz
  • ~-110dBc/Hz @ 100kHz
  • 16X divider
  • fclk = 236MHz

Can show that jitter is the same for the ring PLL and the LC

  • scillator

Can jitter be improved with micromachining? Can accuracy be addressed with tunable component?

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CMOS Micromached Varactors and Inductors

Prototype Development

  • TSMC 0.18µm MM/RF process
  • Post process in SSEL with PAD Etch IV
  • Realize suspended inductors from

interconnect and varactors from MiM and M5- M6 interconnect to achieve high-Q variable tank for low jitter and frequency trimming support

Suspended Inductor

  • Some minor etching of inductor

metal observed

  • No field etching observed
  • Inductor appears suspended
  • Also investigated use of PGS
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Inductor Test Results

0.2 0.5 1 2 j0.2

  • j0.2

j0.5

  • j0.5

j1

  • j1

j2

  • j2

6nH designs

0.2 0.5 1 2 j0.2

  • j0.2

j0.5

  • j0.5

j1

  • j1

j2

  • j2

8nH designs

0.2 0.5 1 2 j0.2

  • j0.2

j0.5

  • j0.5

j1

  • j1

j2

  • j2

10nH designs

Test approach

  • Probe using an Cascade RF-1 probe station
  • Test using an Agilent 8753ES network analyzer
  • Short-open-load (SOL) cal. of ACP-40-GSG-100
  • Measure S11 and convert to Y11
  • De-embed parasitic pad capacitance

Standard Suspended Suspended with PGS

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Suspended Inductor Test Results

  • Calculate Q from de-embedded Y11 parameters using:
  • Observed up to 13% increase in Q
  • PGS did not increase Q

6nH Inductors

1 2 3 4 5 6 7 8 9 1 2 3 4 5

Frequency (GHz) Quality Factor

Standard Released Released with PGS

8nH Inductors

1 2 3 4 5 6 7 8 1 2 3 4 5

Frequency (GHz) Quality Factor

Standard Released Released with PGS

10nH Inductors

1 2 3 4 5 6 7 8 1 2 3 4

Frequency (GHz) Quality Factor

Standard Released Released with PGS

) Re( ) Im(

11 11

Y Y Q =

Standard Suspended Suspended with PGS

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MEMS Varactor Test Results

  • MiM 4-by-4 varactor array
  • Trench cleared very well
  • No etch in field
  • M5-M6 varactor also developed

(aspect ratio too large to be practical)

M5-M6 dielectric etched, but MiM dielectric does not etch at all!

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Results from CMOS Passive RF MEMS

  • Inductor suspension technique successful
  • PGS technique not appropriate for target inductor sizes
  • Need new varactor approach

– M5-M6 varactors are too large due to large gap

  • Why use a varactor?

– To increase frequency accuracy by introducing trimming mechanism

  • Why use MEMS?

– Junction and MOS varactors are lower Q – MiM structure is accurate and bias/temperature stable

  • Is there another way?

– Use MiM and tune with a different technique – shown next

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Frequency Modulation via Harmonic Work Imbalance

RL L Cf RC Resonant tank, LC

  • gm

+ _ + _

v

+ _

Transconductance amplifier + bias Ibias generation

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  • Consider current into and

voltage across net tank capacitance

  • Transconductance amplifier

sustains oscillation by injecting current into the resonant tank

  • Causes work imbalance;

modulates the oscillation frequency

  • Work imbalance is a strong

function of bias current (gm), thus bias current can be utilized to trim absolute frequency

1 1.5 2 2.5 3 3.5 4

  • 15
  • 10
  • 5

5 10 15 t (ns) iC(t) (mA) 1 1.5 2 2.5 3 3.5 4

  • 600
  • 400
  • 200

200 400 600 vC(t) (mV)

gm-amp injects current

  • nto net capacitance

Waveform is distorted

Frequency Modulation via Harmonic Work Imbalance

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Characteristic

  • f fo(gm)
  • fo(gm) is always of the shape shown below
  • gmo corresponds to minimum the gm required for start-up (no distortion)
  • gmsat corresponds to the point at which gm is so large that current injection
  • nto the tank cap. approaches an impulse (maximum waveform distortion)
  • fo ← gm ← I, where I is the current in the transconductance amplifier
  • Bias current, I, can be made temperature dependent

fo gm gmo gmsat

No

  • scillation

fmax fmin

P mo

R g 1 =

NOTE: Where RP is the total equivalent parallel loss across the tank

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Radio Frequency Oscillator Core

  • Complementary cross-

coupled configuration

  • PMOS tail for low flicker

noise upconversion

  • Devices in red are isolated

with deep NWELL option

  • MiM capacitors configured

for release (if chemistry is ever determined)

  • 900MHz target frequency

6nH 8.3pF 8.3pF 100 0.18 100 0.18 40 0.18 40 0.18

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Discrete Clock Synthesizer Architecture

  • RF core drives a high bandwidth amplifier which squares the signal

and decreases the rise/fall times

  • D flip-flops serve as frequency dividers
  • 50Ω buffers required for off-chip instrumentation

DFF Q Q D

AMP +

  • DFF

Q Q D DFF Q Q D

50Ω 50Ω 50Ω

…

fo fo 2 fo 4 fo 8 fo 2n

…

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50 of 79 Prototype clock synthesizer in TSMC 0.18µm MM/RF

Fabricated Discrete Clock Prototypes

Device packaged in 16-pin dual-inline package (DIP) Test printed circuit board (PCB) for environmental testing Preliminary wafer testing with Cascade RF-1

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Results: Short-Term Frequency Stability

  • Jitter measured using stats mode of a Tektronix CSA11801A DSO
  • 50,000 samples acquired at each edge
  • DUT RMS jitter (x14.1 for p-p):

ppm ps J J J DUT 55 97 . 1

2 1 2 2

= = − =

28MHz clock edge 1 28MHz clock edge 2

NOTE: the p-p 1x10-9 jitter for XTAL

  • scillators around

30MHz is ~50ps This work: ~27.8ps

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Results: Accuracy, Precision, and Trimming Range

Frequency accuracy/precision

  • Design target = 900MHz
  • Measured mean = 891.4MHz
  • Inaccuracy = 0.96%
  • Precision = ±0.75% around mean

886 888 890 892 894 896 898 900 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Die Number Frequency (MHz)

Trimming Range

  • Available range is 2.2% for trimming
  • Captures 900MHz target

886 888 890 892 894 896 898 900 902 904 906 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

Current Mirror Bias (mA) Frequency (MHz)

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Temperature Drift

  • Trimmed oscillator core to 900MHz at

room temperature

  • Total TC +0.67% to -0.89% with no

compensation (very good and linear)

  • fTC dominated by TC of real loss in

inductance

  • Complete relationship has been

derived

  • TC can be compensated via a variety
  • f mechanisms
  • Conclusion: free-running LC reference
  • scillators exhibit low drift over PVT
  • Next step: develop into µsystem with

additional support

Frequency vs. Temperature

890.00 892.00 894.00 896.00 898.00 900.00 902.00 904.00 906.00 908.00

  • 40
  • 20

20 40 60 80 100

Temperature (°C) Frequency (MHz)

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Low-Latency Glitch-Free Frequency Switching for µsystem

  • The clock ref. for the µsystem synthesizes signals from 1.1GHz to 2kHz
  • With top-down free-running architecture, frequency can be switched with

very low latency

  • Must consider glitches
  • Use synchronizers to prevent meta-stable state

CLK1 SELECT CLKout glitch CLK2

DFF Q D DFF Q D 2fmax S0 S1 S2 S3 fmax fmax/2 fmax/22 fmax/23 fmax/215 fout

. . .

…

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µsystem Test and Measurement Set-Up

Micrograph of fabricated µsystem

  • TSMC 0.18µm MM/RF
  • ~3.5 million transistors
  • 12.8mm2 (clock = 0.3mm2 or < 3%)

Test and measurement Set-up

  • HP82000
  • Tektronix CSA11801A
  • Agilent E4405B
  • Packaged test chip

Memory Peripherals Memory Pipeline Memory Loop Cache AFE CLK

CSA11801A E4405B HP82000 Packaged test chip

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Results: Low-Latency Glitch-Free Frequency Switching

  • Case 1: Switching from 1MHz to 33MHz
  • Case 2: Switch rapidly from 4 to 8 to 16 to 33MHz
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Results: Short-Term Frequency Stability

Concern

  • How does processor switching

affect short-term stability?

Case 1: 33MHz

  • Only clock tree switches

Case 2: 33MHz

  • Processor runs loop code

Results

  • Less than 1dB degradation
  • bserved at 10kHz
  • Increased spurious power observed

(3.5ps to 4.5ps jitter)

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Summary of Results

  • Demonstrated a CMOS-compatible passive RF MEMS

fabrication process (varactor not used)

  • Demonstrated a high accuracy and ultra low jitter

monolithic clock reference

  • Demonstrated that free-running LC oscillators exhibit low

drift over PVT (and can be improved)

  • Demonstrated top-down clock in µsystem and low-latency

frequency switching for power management

  • Demonstrated that substrate noise injection due to

switching in µsystem does not affect clock performance substantially

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Mobius’ Clock Synthesis Technology

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General Approach

  • Cost

– Abandon use of all MEMS technology – Migrate to vanilla logic processes (i.e. 1P4M, 2P4M, etc.)

  • Technology

– Focus on achieved performance in CMOS and techniques by which it can be improved – Utilize RF LC reference and frequency divide to achieve low jitter – Calibrate frequency with capacitor bank and develop automatic calibration hardware – Use circuit techniques to compensate frequency drift over PVT

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RF-TCHO™: Mobius’ Monolithic Clock Synthesis Technology

Simplified schematic of Mobius’ Radio Frequency Temperature Compensated Harmonic Oscillator (RF-TCHO™) technology

bp-1,…,b0 generation Automatic frequency calibration macro

  • gm

+ _ + _

v

+ _

Transconductance amplifier + I(T) bias I(T) generation RL L Cf RC ~1-2GHz Resonant tank, LC vctrl(T) generation fo(T) compensation module, Cv+f(T) Cv+f(vctrl) Cv+f(vctrl) Process variation comp. module, Cf(bp-1,…,b0) Resonant Frequency correction, Cf(bp-1,…,b0) fcal

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RF-TCHO™ Transconductance Amplifier + I(T) Bias

RL L Cf RC ~1-2GHz Resonant tank, LC

  • gm

+ _ + _

v

+ _

Transconductance amplifier + I(T) bias I(T) generation

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First Order Model for Predicting fo

) ( 1 2 1

amp

C C L f

f

  • +

≈ π

  • Expression above is the classic LC oscillator frequency expression

where the reactance (phase) is zero

  • Typically L and C have negligible temperature coefficients (TCs)
  • Ignoring RL and RC, fo does not depend on temperature
  • Camp is the capacitive load presented by the transistors in the

gm-amplifier

  • Expression above is only ≈ 5% accurate
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Second Order Model for Predicting fo(T)

L T R C C L T R C C C C L T f

C

amp f L amp f amp f

  • −

+ − + + ≈ ) ( ) ( ) ( ) ( * ) ( 1 2 1 ) (

2 2

π

  • RL and RC introduce a phase shift across the LC network;

thus, the frequency expression is modified (solved by finding zero phase of the new network)

  • RL and RC represent real losses which have temperature

coefficients; thus, fo is a function of T

  • Note, in this model, if RL and RC are exactly equal and have

the same TC, then fo(T) is constant for all T

  • Expression above is ≈ 1-2% accurate
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Frequency Modulation due to Harmonic Work Imbalance

  • Amplifier sustains oscillation by injecting energy (current) into the resonant tank
  • Capacitor absorbs nearly all energy (current in L can’t change instantaneously)
  • Causes harmonic work imbalance between L and C; fo lowered to reconcile imbalance
  • Induced frequency modulation varies over temperature and bias conditions
  • Temperature dependent reference, I(T), stabilizes fo(T) due to harmonic work imbalance

1 1.5 2 2.5 3 3.5 4

  • 15
  • 10
  • 5

5 10 15 t (ns) iC(t) (mA) 1 1.5 2 2.5 3 3.5 4

  • 600
  • 400
  • 200

200 400 600 vC(t) (mV)

gm-amp injects current

  • nto net capacitance

33 33.5 34 34.5 35 35.5 36

  • 20
  • 15
  • 10
  • 5

5 10 15 20 Current (mA) 33 33.5 34 34.5 35 35.5 36

  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.2 0.4 0.6 0.8 Time (ns) Voltage (V) T = -40C T = 30C T = 100C

Waveform is distorted Distortion is temperature/bias dependent and can be utilized for fo(T) compensation

Increasing T

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Frequency (fo) Generation

1 Y I(T) L(T) RL (T) Cf (T) Cv(T) RC (T)

M1 M2 M3 M4

  • I(T) is a

composite signal

  • f PTAT, PTAT2,

and/or CTAT current generators which stabilize fo(T)

  • 1:Y mirror

reduces power dissipated in reference leg

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RF-TCHO™ I(T) Bias Generation

  • I(T) is generated by combining

temperature-dependent reference currents

  • Temperature-dependent

reference currents can be generated with many different topologies

  • The shape of I(T) is determined

by the relative magnitude of each temperature-dependent current source

  • I(T) often does not permit the

complete removal of fo(T), but it can always be used to help stabilize fo(T)

IPTAT IPTAT

2

ICTAT 1 S I(T) Current Mirror

T I

ICTAT

T I

IPTAT

T I

IPTAT

2

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RF-TCHO™ Temperature Compensation, Cv+f(T)

  • gm

+ _ + _

v

+ _

Transconductance amplifier + I(T) bias I(T) generation RL L Cf RC ~1-2GHz Resonant tank, LC vctrl(T) generation fo(T) compensation module, Cv+f(T) Cv+f(vctrl) Cv+f(vctrl)

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RF-TCHO™ Temperature Compensation, Cv+f(vctrl)

1Cv 1Cf b0 2x-1Cv 2x-1Cf bx-1 vctrl(T) To one side of the resonant tank

  • fo(T) is difficult to predict

without measured Si due to limited modeling

  • Make fo(T) correction

programmable and select the correct compensation factor post-fabrication

  • Use an x-bit bank of

AMOS/IMOS varactors in parallel with the fixed tank capacitance and switch the ratio between the two

  • Control varactors with a

temperature dependant control voltage, vctrl(T), and create a temperature dependant capacitance, Cv+f(T) VDD VDD

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Third Order Model for Predicting fo(T,VDD)

) ( ) ( ))] ( ( ) ( ) ( [ ) ( ) ( ))] ( ( ) ( ) ( [ * ))) ( ( ) ( ) ( )( ( 1 2 1 * )) , ( 1 ( ) (

2 2

T L T R T v C T C T C T L T R T v C T C T C T v C T C T C T L V T T f

C

ctrl v amp f L ctrl v amp f ctrl v amp f DD

  • −

+ + − + + + + − ≈ π δ

Correction factor accounting for temperature dependent harmonic work imbalance Fixed tank capacitance and capacitance from MOS devices in the transconductance amplifier (minimal temperature dependence) Fixed tank inductance (minimal temperature dependence) Variable tank capacitance used maintain frequency accuracy over temperature Parasitic resistive losses in series with the tank inductance and capacitance Expression above can be better than 0.1% accurate with appropriate models

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What is δ(T,VDD)?

  • A method of harmonic balance can be used to determine

δ(T,VDD)

  • hi(n) is the nth Fourier coefficient of the current

waveform, i(t), injected into the tank normalized to the Fourier coefficient of the fundamental

  • Note, if hi(n) = 0 for all n ≥ 2, then fo is temperature and

bias independent in relationship to harmonic work imbalance

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − =

∑

∞ −2 2 ) ( 2 2 2

)) , ( ( 1 2 1 ) , (

n DD n i DD

V T h n n Q V T δ

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RF-TCHO™ Process Variation Comp., Cf(bp-1,…,b0)

  • gm

+ _ + _

v

+ _

Transconductance amplifier + I(T) bias I(T) generation RL L Cf RC ~1-2GHz Resonant tank, LC vctrl(T) generation fo(T) compensation module, Cv+f(T) Cv+f(vctrl) Cv+f(vctrl) Process variation comp. module, Cf(bp-1,…,b0) Resonant frequency correction, Cf(bp-1,…,b0)

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RF-TCHO™ Process Variation Comp., Cf(bp-1,…,b0)

1Ctrim b0 2p-1Ctrim bp-1 1Ctrim b0 2p-1Ctrim bp-1 Parallel binary-weighted fixed capacitor banks

To resonant tank

  • Large W/L required to keep

Ron small

  • W/L large → large Cdb →

increase finger count

  • Still often problems with

large Ctrim → split Ctrim

  • Binary-weighted capacitor array adds/subtracts switched

capacitance and modulates frequency

  • Simple concept, but many complicated details
  • Recently developed proprietary “switchless” trimming

Ctrim Cdb bp W/L

  • Constant R & TC load

problems (use dummies) Ctrim bp Cdummy bp

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Automatic Frequency Calibration Macro (AFC™)

  • gm

+ _ + _

v

+ _

Transconductance amplifier + I(T) bias I(T) generation RL L Cf RC ~1-2GHz Resonant tank, LC vctrl(T) generation fo(T) compensation module, Cv+f(T) Cv+f(vctrl) Cv+f(vctrl) Process variation comp. module, Cf(bp-1,…,b0) Resonant frequency correction, Cf(bp-1,…,b0) bp-1,…,b0 generation Automatic frequency calibration macro fcal

AFC™ generates bp-1, …, b0 based on calibration frequency

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Sample Customer Application

  • FS-USB to RS-232 Bridge

Controller

– Application: Cables to bridge PC USB ports to mobile devices – Specification: 48MHz ± 0.25% over PVT and <20ps p-p jitter – Existing implementation: 12MHz XTAL and 4X PLL

  • With Mobius’ RF-TCHO Macro

– Eliminate PLL + XTAL – 1.536GHz reference oscillator – PG in November: Chartered 0.35µm 2P4M – Within specification over PVT

Before: FS-USB to RS-232 Bridge Controller (chip shown in USB cell phone cable) After: FS-USB to RS-232 Bridge Controller (chip shown

  • n test board)
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Test Results

  • ±0.25% accuracy achieved
  • ver PVT

(for T = -40 to 80C)

  • Record total accuracy in Si
  • Essentially, developed an

all-CMOS time reference

  • Can be utilized to

synchronize other less accurate Si references

Frequency vs. Temperature for Calibrated Mobius FS- USB RF-TCHO Clock

47.85 47.9 47.95 48 48.05 48.1 48.15

  • 40
  • 20

20 40 60 80 Temperature (C) Frequency (MHz) VDD=LO VDD=HI Low Specification High Specification

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Future Work and Summary of Results

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Future Work

  • Continue to demonstrate fast, RF-referenced, ultra-low

jitter, and high-accuracy integrated clock generators and timing references in CMOS with “hard core” RF/analog techniques

  • Move from a record-setting total PVT accuracy of ±0.25%

toward better than ±500ppm in CMOS

  • fTC still very difficult to predict (now programmable)
  • Continue to investigate emerging timing and frequency

synthesis technologies, but MEMS technologies currently do not appear to be economically viable and suffer from performance challenges

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Summary of Results

  • Exciting research and commercial activity in

monolithic timing and frequency synthesis

  • MEMS technologies require better economic

analysis (i.e. application, cost, market, and business model) to determine market viability

  • With creative concepts in circuit design, CMOS

continues to address integration demand at low cost

  • Is MEMS really solving a problem in frequency

synthesis? Must answer this question before developing new technologies