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List of content Energy efficient thermal packaging 1. Introduction - - PDF document

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Chalmers University of Technology Chalmers University of Technology List of content Energy efficient thermal packaging 1. Introduction to thermal issues 2. Introduction to electronics packaging Johan Liu 3. Solutions to achieve energy

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Chalmers University of Technology

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Energy efficient thermal packaging

Johan Liu Department of Microtechnology and Nanosciences, Chalmers University of Technology, Gothenburg, Sweden April 27,2012 Email:jliu@chalmers.se Lecture for the Course: DAT235 Energy Aware Computing

Chalmers University of Technology

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List of content

  • 1. Introduction to thermal issues
  • 2. Introduction to electronics packaging
  • 3. Solutions to achieve energy efficient thermal

packaging

  • Thermal interface material for efficient heat

transfer

  • Energy efficient cooling fins
  • 3D Through Silicon Via solution for efficient

thermal path

  • High thermal performance interconnect

Chalmers University of Technology

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  • 1. Introduction to thermal issues

Moores Law (http://www.pkal.org/documents/Pulle yblank_MooresLaw.pdf)

ULSI Heat density: 100W/cm2, Hotspot: 400W/cm2，Until 2020, Number of In‐ and Outputs more than 6000 on CPU.

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SLIDE 2
  • 5-

Power dissipation increases

Increasing power density and lowered/maintained junction temperature and leads to emphasized need for improved thermal control and cooling (ITRS)

  • 6-

Examples of electronic and microsystem products where large cooling capacity is needed

Direct chip cooling (100-400 W/cm2) High Power LED (2000-3000 W/cm2) RF MEMS (40-50 W/cm2) Automotive power electronics (80W/cm2) Optoelectronics module (100W/cm2)

  • 7-

Over 50% of electricity is used for cooling of dataservers in US 2006, Ref: Eric Pop, “Energy dissipation and transport in nanoscale devices,” Nano Research, vol. 3, Mar. 2010,

  • pp. 147-169.

Cooling consumes lots of energy

  • 8-

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  • 2. Introduction to electronics packaging
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SLIDE 3

Electronics Packaging

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Wire bond

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Flip chip

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Tape Automated Bonding (TAB) Process

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SLIDE 4

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System in Package (SIP) Lower Core board

Embedded capacitor Embedded resistor

FC Die

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  • 3. Solutions to achieve energy

efficient thermal packaging

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Thermal management Solutions

  • Heat pipes
  • Thermal Interface Materials (TIMs)
  • Direct cooling using liquid and air
  • Thermo-electrical cooling

TIM

???

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Micro – and Nanotechnology based energy efficient thermal packaging solutions for electronics

CNT-Thorough Silicon Via (TSV) for vertical heat dissipation Carbon NanoTube (CNT) cooling fins CNT interconnent for heat dissipation Nano-polymer metal composite as thermal interface material for heat dissipation Conventional cooling

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SLIDE 5

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Thermal interface material for efficient heat transfer Thermal Interface Materials (TIM) – Current Situation

Polymer composites

  • Polymer matrix and high

thermal conductivity particulate filler

  • Thermal transport through

percolating network

  • Thermal conductivity typically

limited to 2 – 6W/mK

  • Inadequate thermal

performance

Solder

  • Melting point 150 – 240°C
  • High thermal conductivity up to 20

W/mK

  • Significant reliability considerations

and high volatile price

  • Typically Indium (MP 157°C)
  • Limited use for large die size

Concept for development of nano polymer- metal composite as thermal interface material (Nano-TIM)

Metal Polymer composites e g. gel, wax, silicon, epoxy and metal particles (Nano-TIM)

 Two interpenetrating phases  Heat conduction through high thermal conductivity metal phase  Geometry and composition defined by polymeric phase

Nano polymer-metal composite as thermal interface material (Nano-TIM)

Fibrous nanopolymer Network

Low Melting Temperature Metal Schematic IHS Die

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Nano‐TIM based on nanopolymer metal composite technology

  • ~8‐28 W/mK bulk

thermal conductivity by ASTM D5470 and Xenon flash methods

  • Very thin BLT

(adjustable from 10‐ 150µm) – low thermal resistance

Nano‐TIM based on nanopolymer metal composite technology

Efficient heat dissipation of large power LED devices using Nano-Thermal Interface Material

NanoTIM (SHT6050)

  • vs. TC5022

High power LED High power LED TIM Heatsink+Fan

Parameters Grease Nano-TIM Applied effect

24W 24W

Substrate temperature (max fan speed, @RT)

36°C 30°C

Rth = ΔT/Q [K/W]

0.46 0.21

Relative resistance

100% 45% Display panel SMART TIM FOR PERFORMANCE SMART TIM FOR ENERGY SAVING

10 20 30 40 50 60 70 80 90 100 2 4 6 8 10 12

Active cooling energy [%] Temperature increase [°C]

Cooling Power reduced 50%

  • -> Increase T by ~2.25°C

Energy saving = 77%

SHT160

SMARTTIM

Graphite TIM

Saving Energy by Reducing Cooling Power

OR..

SHT160

SMARTTIM

OR..

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Graphene grown on Cu, and SiO2 substrate

Graphene as heat spreader

(Thermal conductivity of graphene: 8000 W/mK)

Illustration of a typical packaged component of the integrated cooling device with TIMs (g&h) and graphene layer at the hot spots (f): (a) IC chip, (b) heat sink, (c) lid, (d) chip carrier, (e) interconnects, (f) graphene layer, (g&h) nano TIM, (i) heat flow direction (top and bottom side of the device).

Integrated passive cooling using Graphene as heat spreader and TIM

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Energy efficient cooling fins

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  • Seamless rolled‐up graphene

layers

  • Chirality represented by indices

(n, m) – n=m, armchair – m=0, zigzag – Otherwise, chiral

  • Two categories:

Single‐ (SWNTs, by Iijima in 1994) & Multi‐walled carbon nanotubes (MWNTs, by Iijima in 1991)

Carbon nanotubes (CNTs): structure

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Chirality

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SLIDE 8

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Carbon NanoTube as cooling fins Water Assisted CNT On-chip Cooling

  • CNT cooler vs Si cooler

– Forced Air convection, flow rate=170 ml/min – Power on chips from 0.2 W to 2.22 W – Hotspot power density: above 1500 W/cm2 At a certain temperature (e.g. T=55 C), compare the power dissipated by CNT and Si cooler, get (PCNT-PSi)/Psi=44.07%

Video show of CNT based cooling system

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High performance heat dissipation using water assisted CNT based cooling system

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Method Heat flux (W/cm2) Density factor (1/cm2) Fluid velocity (ml/min) Efficiency

Tuckerman D. et al.,

  • Electron. Dev. Lett. 2, 1981

Water assisted Silicon fins 790 1 516 Temperature increase under heating: 71 K Jiang L. et al., IEEE Trans.

  • Compon. Packag. Technol.

25, 2002 Water assisted Silicon fins 38 1 9 Temperature increase under heating: ~75 K Zhang H. et al., IEEE Trans.

  • Compon. Packag. Technol.

28, 2005 Water assisted Aluminum fins 189 1 1002 Temperature decreased by: 11 K Colgan E. et al., IEEE

  • Trans. Compon. Packag.
  • Technol. 30, 2007

Water assisted Silicon fins 300 1 ~1500 Temperature increase under heating: <40 K Chowdhury I. et al., Nat.

  • Nanotechnol. 4, 2009

Thermoelectrical cooling 1300 ~256 / Temperature decreased by: 15 K Dang B. et al., IEEE Trans.

  • Adv. Packag. 33, 2010

Water assisted Silicon fins 45 1 104 Temperature decreased by: 36 K Kordas K. et al., Appl.

  • Phys. Lett. 90, 2007

Nitrogen assisted CNT fins ~420 1 2000 Temperature decreased by: 46 K Fu Y. et al. Water assisted CNT fins 5000 320 17 Temperature decreased by: 40 K

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Reliability of the CNT-based cooling system

Reliability test results of the CNT based cooling system. (A) Cooling performance test system. (B) The CNT based cooling in the testing

  • system. (C) Cooling performance of the cooler before the temperature

cycling test. (D) Cooling performance of the cooler after the temperature cycling test.

Verification of water that flows into the CNT Cooling system.

(A) As-grown CNT Cooler. (B) CNT Cooler immersed in water. Air bubbles are released from CNT forest. (C) CNT immersed in water. (D-I) CNT fins are taken out from water and dry naturally in air. Images are captured every one minute. (J) CNT fins are put back into water. Scale bar: A and B, 100 μm. C-J, 50 μm.

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3D Through Silicon Via solution for efficient thermal path

CNT TSV for Vertical Heat Dissipation

(K. SAKUMA et al., IBM J. RES. &

  • DEV. NOV. 2008)
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CNT based lithogrpahic processes

Etching of high aspect ratio Si vias Depostion of catalyst layer Growth of CNTs Depostion of supporting layer Grinding/polishing

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As-grown CNT bundles from the bottom of Si vias Stacked CNT bundles: CNT-CNT interface for 3D interconnection CNT bundles fastened onto Au: CNT-Au interface (eg. for flip-chip interconnection) Surrounding Si dry etched to reveal the hidden CNT structures

3D chip stacking TSVs Using CNT

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Densified CNT- Filled TSV for 3D Thermal Management

  • Transfer densified carbon nanotube bundles into TSVs

to

– Lower the thermal and electrical resistances of the vias – Lower the process temperature to ~ 200 ºC

  • A combination of densification, transfer, and

planarization of CNT bundles realized

  • Four probe measurement shows these vias are with

resistances in the range of 2 – 3 Ω

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High thermal performance interconnect

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SLIDE 11

Round CNT interconnects grown in an array pattern. Rectangular CNT interconnects grown simultaneously on the Si substrate and copper lines in a peripheral pattern Rectangular CNT interconnectbu grown simultaneously on the Si substrate and copper lines, in an array pattern

Carbon Nanotube Interconnect for thermal management

4 µm CNT pitch

Processes developed (cont.)

Carbon Nanotube Interconnect for thermal management