LISA: Machine Description Language Language Jared Wood Outline - - PowerPoint PPT Presentation

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LISA: Machine Description Language Language Jared Wood Outline - - PowerPoint PPT Presentation

Nov 12, 2023 207 likes •551 views

LISA: Machine Description Language Language Jared Wood Outline LISA Motivation Description Description Machine model Requirements Operation sequencer L-charts LISA: Motivation Accurate machine model

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SLIDE 1

LISA: Machine Description Language Language

Jared Wood

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SLIDE 2

Outline

  • LISA

– Motivation – Description – Description – Machine model

  • Requirements
  • Operation sequencer

– L-charts

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SLIDE 3

LISA: Motivation

  • Accurate machine model

– Bit- & cycle-/phase-accuracy

  • Models:
  • Models:

– ISA for compilers & instruction-set simulators

  • Too rough

– HW design

  • Too detailed
  • LISA: cover gap between models
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SLIDE 4

LISA: Motivation

  • Behavioral pipeline modeling

– Pipeline controller for generic machine model – Parameterized by – Parameterized by

  • Precedence constraints
  • Resource constraints
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LISA: Description

  • Operation-level description of pipeline
  • Operations: register transfers during single

control step control step

  • Instructions: set of operations
  • Control step:

– Instruction-cycle – Clock-cycle – Phase-cycle

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SLIDE 6

LISA: Description

  • Operation schedulingL-Charts

– Specify:

  • Time and resource allocation
  • Time and resource allocation
  • Operation sequencer w/ ASAP strategy
  • Goal:

– Single generic machine model – Single generic description language

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SLIDE 7

LISA: Description

  • Main applications so far:

– Timed ISA simulation for HW/SW co-design

  • Other possibility:
  • Other possibility:

– Compilation

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SLIDE 8

LISA: Description

behavior Select/schedule instructions compiler Scheduled instructions behavior simulator

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SLIDE 9

Machine Model: Requirements

  • Application domain:

– RT SW design – DSP/embedded system design – DSP/embedded system design – HW/SW co-verification – Architecture exploration

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SLIDE 10

Machine Model: Requirements

  • Processor class:

– DSPs & microcontrollers

  • Low or medium complexity
  • Low or medium complexity
  • Pipelined, VLIW, & RISC architectures
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SLIDE 11

Machine Model: Requirements

  • Model accuracy:

– Timing:

  • Instruction, clock, or phase

– Bit-accurate register transfers – Bit-accurate register transfers – Exact state modeling:

  • Pipeline, interrupt, & wait

– Spatial accuracy:

  • SW-level: registers, memory
  • System-level: interrupts, peripherals
  • HW-level: pins

– Control step state visibility

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SLIDE 12

Machine Model: Operation Sequencer

  • At control step t:

– Admissible operations determined

  • Based on precedence & resource constraints
  • Based on precedence & resource constraints

– Transition function Ft formed – Ft applied to machine – Machine state changes

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SLIDE 13

Machine Model: Operation Sequencer

Instruction n-1 {O1,O2,O3} Instruction n {P1,P2,P3} Instruction n+1 {Q1,Q2,Q3}

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SLIDE 14

Machine Model: Operation Sequencer

Instruction n-1 {O1,O2,O3} Instruction n {P1,P2,P3} Instruction n+1 {Q1,Q2,Q3} precedence

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SLIDE 15

Machine Model: Operation Sequencer

Instruction n-1 {O1,O2,O3} sequencer Instruction n {P1,P2,P3} Instruction n+1 {Q1,Q2,Q3}

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SLIDE 16

Machine Model: Operation Sequencer

Instruction n-1 {O1,O2,O3} rules Admissible sequencer Instruction n {P1,P2,P3} Instruction n+1 {Q1,Q2,Q3} Admissible

  • perations

Ft = {O3,P2,Q1}

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SLIDE 17

L-Charts

  • Extended Gantt chart

– Change time axis to precedence axis

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SLIDE 18

L-Charts

R0: O1 R1: O2 R2: O3 precedence R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 19

L-Charts

R0: O1 R1: O2 R2: O3 precedence sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 20

L-Charts

R0: O1 R1: O2 R2: O3 precedence R0: O1 sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2 R0: O1 R1: R2:

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SLIDE 21

L-Charts

R0: O1 P1 R0: O1 R1: O2 R2: O3 precedence R0: O1 P1 R1: O2 R2: sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 22

L-Charts

R0: O1 P1 Q1 R0: O1 R1: O2 R2: O3 precedence R0: O1 P1 Q1 R1: O2 P2 R2: O3 sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 23

L-Charts

R0: O1 P1 Q1 R0: O1 R1: O2 R2: O3 precedence R0: O1 P1 Q1 R1: O2 P2 P3 R2: O3 P4 sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 24

L-Charts

R0: O1 P1 Q1 R0: O1 R1: O2 R2: O3 precedence R0: O1 P1 Q1 R1: O2 P2 P3 R2: O3 P4 Q2 sequencer R0: P1 R1: P2 P3 R2: P4 R0: Q1 R1: R2: Q2

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SLIDE 25

L-Charts

  • LISA expressed more compactly

O1(R1) | O2(R2) | O3(R2) | O4(R3),O5(R4) | O6(R4)

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SLIDE 26

L-Charts

  • LISA expressed more compactly

O1(R1) | O2(R2) | O3(R2) | O4(R3),O5(R4) | O6(R4) | precedence , parallelism ( ) resource

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SLIDE 27

L-Charts

  • LISA expressed more compactly

O1(R1) | O2(R2) | O3(R2) | O4(R3),O5(R4) | O6(R4) | precedence , parallelism ( ) resource No precedence

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SLIDE 28

L-Charts

  • Pipelined architecture

– 3 types of hazards

  • Structural: resource conflicts
  • Data: data grabbed before update
  • Data: data grabbed before update
  • Control: conflict assigning proper control step

– Must be detected & resolved

  • Gantt naturally covers structural
  • Operations accessing resource must specify R/W
  • Access must be announced in advance
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SLIDE 29

L-Charts

  • Additional extension
  • Hazard scenario

Instruction 1: IF | ID(!w:R0) | IA | ID(w:R0) | Instruction 2: IF | ID(r:R0) | IA | IE

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SLIDE 30

L-Charts

  • Additional extension
  • Hazard scenario

Instruction 1: IF | ID(!w:R0) | IA | ID(w:R0) | Instruction 2: IF | ID(r:R0) | IA | IE Data hazard not admissible

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SLIDE 31

L-Charts

  • Additional extension
  • Hazard scenario

Instruction 1: IF | ID(!w:R0) | IA | ID(w:R0) | Instruction 2: IF | nop | nop | ID(r:R0) | IA | IE

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SLIDE 32

L-Charts

  • Pipeline flow delayed only for resource

conflicts

  • Processors w/ out-of-order executions
  • Processors w/ out-of-order executions

excluded

– No superscalar processors – Instuction n checked with instruction n-1

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SLIDE 33

Conclusion

  • Main contribution of LISA

– L-charts

  • Extend Gantt charts to handle data/control hazards
  • Mainly used in simulation
  • Mainly used in simulation
  • Capable to use in compilation
  • Aimed at

– low/medium complexity machine

  • DSP/embedded system

– HW/SW co-design