Lectures for 3rd Edition Note: these lectures are often - - PowerPoint PPT Presentation

Lectures for 3rd Edition

1

2004 Morgan Kaufmann Publishers

Note: these lectures are often supplemented with other materials and also problems from the text worked out

• n the blackboard. You’ll want to customize these

lectures for your class. The student audience for these lectures have had exposure to logic design and attend a hands-on assembly language programming lab that does not follow a typical lecture format.

Chapter 1

2

2004 Morgan Kaufmann Publishers

Introduction

• This course is all about how computers work
• But what do we mean by a computer?

– Different types: desktop, servers, embedded devices – Different uses: automobiles, graphics, finance, genomics… – Different manufacturers: Intel, Apple, IBM, Microsoft, Sun… – Different underlying technologies and different costs!

3

2004 Morgan Kaufmann Publishers

– Different underlying technologies and different costs!

• Analogy: Consider a course on “automotive vehicles”

– Many similarities from vehicle to vehicle (e.g., wheels) – Huge differences from vehicle to vehicle (e.g., gas vs. electric)

• Best way to learn:

– Focus on a specific instance and learn how it works – While learning general principles and historical perspectives

Why learn this stuff?

• You want to call yourself a “computer scientist”
• You want to build software for people use (need performance)
• You need to make a purchasing decision or offer “expert” advice
• Both Hardware and Software affect performance:

– Algorithm determines number of source-level statements

4

2004 Morgan Kaufmann Publishers

– Language/Compiler/Architecture determine machine instructions (Chapter 2 and 3) – Processor/Memory determine how fast instructions are executed (Chapter 5, 6, and 7) – I/O system determine how fast I/O operations may be executed (Chapter 8)

• Assessing and Understanding Performance in Chapter 4

What is a computer?

• Components:

– input (mouse, keyboard) – output (display, printer) – memory (disk drives, DRAM, SRAM, CD) – network

• Our primary focus: the processor (datapath and control)

– implemented using millions of transistors

5

2004 Morgan Kaufmann Publishers

– implemented using millions of transistors – Impossible to understand by looking at each transistor – We need...

Abstraction

• Delving into the depths

reveals more information

• An abstraction omits unneeded detail,

helps us cope with complexity

• Both hardware and software consist

6

2004 Morgan Kaufmann Publishers

• f hierarchical layers, with each lower

layer hiding details from the level above.

High-level language:

• portable (machine-independent) language.

Assembly language:

• A symbolic representation of machine instr.

• A simplified view of hardware and software as hierarchical layers:

Abstraction

7

2004 Morgan Kaufmann Publishers

Operating System Compiler …

How do computers work?

• Need to understand abstractions such as:

– Applications software – Systems software – Assembly Language – Machine Language – Architectural Issues: i.e., Caches, Virtual Memory, Pipelining – Sequential logic, finite state machines

8

2004 Morgan Kaufmann Publishers

– Combinational logic, arithmetic circuits – Boolean logic, 1s and 0s – Transistors used to build logic gates (CMOS) – Semiconductors/Silicon used to build transistors – Properties of atoms, electrons, and quantum dynamics

• So much to learn!

Instruction Set Architecture (ISA)

• A very important abstraction

– interface between hardware and low-level software

• standardizes instructions, machine language bit patterns, etc.

– advantage: different implementations of the same architecture – disadvantage: sometimes prevents using new innovations

9

2004 Morgan Kaufmann Publishers

– True or False: Binary compatibility is extraordinarily important?

• Modern instruction set architectures:

– IA-32, PowerPC, MIPS, SPARC, ARM, and others

Historical Perspective

• ENIAC built in World War II was the first general purpose computer

– Used for computing artillery firing tables – 80 feet long by 8.5 feet high and several feet wide – Each of the twenty 10 digit registers was 2 feet long – Used 18,000 vacuum tubes – Performed 1900 additions per second

10

2004 Morgan Kaufmann Publishers

–Since then:

Moore’s Law:

transistor capacity doubles every 18-24 months

Historical Perspective

–

11

2004 Morgan Kaufmann Publishers

Chapter 2

12

2004 Morgan Kaufmann Publishers

Instructions:

• Language of the Machine
• We’ll be working with the MIPS instruction set architecture

– similar to other architectures developed since the 1980's – Almost 100 million MIPS processors manufactured in 2002 – used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …

1400 1300 Other

13

2004 Morgan Kaufmann Publishers 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 1998 2000 2001 2002 1999 Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM

MIPS Instructions

• MIPS Instruction Types

– Arithmetic – Data transfer – Logical operation – Flow control

• 14

2004 Morgan Kaufmann Publishers

• Design Principles

– Design Principle 1: Simplicity favors regularity. – Design Principle 2: Smaller is faster. – Design Principle 3: Good design demands a compromise – Design Principle 4: Make common cast fast.

MIPS Arithmetic Instructions

• All instructions have 3 operands
• Operand order is fixed (destination first)

Example: C code: a = b + c MIPS ‘code’: add a, b, c

15

2004 Morgan Kaufmann Publishers

MIPS ‘code’: add a, b, c (we’ll talk about registers in a bit) “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple”

MIPS Arithmetic Instructions

• Design Principle 1: simplicity favors regularity.
• Of course this complicates some things...

C code: a = b + c + d; MIPS code: add a, b, c add a, a, d

16

2004 Morgan Kaufmann Publishers

• Operands must be registers, only 32 registers provided
• Each register contains 32 bits
• Design Principle 2: smaller is faster.

Why?

MIPS Arithmetic Instructions

• Register vs. Memory

– Arithmetic instructions operands must be registers, — only 32 registers provided – Compiler associates variables with registers – What about programs with lots of variables?

17

2004 Morgan Kaufmann Publishers

Processor I/O

Control Datapath Memory Input Output

MIPS Arithmetic Instructions

• Memory Organization

– Viewed as a large, single-dimension array, with an address. – A memory address is an index into the array – "Byte addressing" means that the index points to a byte of memory.

8 bits of data

18

2004 Morgan Kaufmann Publishers

1 2 3 4 5 6 ...

8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data

MIPS Arithmetic Instructions

• Memory Organization

– Bytes are nice, but most data items use larger "words" – For MIPS, a word is 32 bits or 4 bytes.

4

32 bits of data 32 bits of data

Registers hold 32 bits of data

19

2004 Morgan Kaufmann Publishers

– 232 bytes with byte addresses from 0 to 232-1 – 230 words with byte addresses 0, 4, 8, ... 232-4 – Words are aligned i.e., what are the least 2 significant bits of a word address?

8 12 ...

32 bits of data 32 bits of data

Registers hold 32 bits of data

MIPS Data Transfer Instructions

• Data Transfer Instruction: Load and store instructions
• Example:

C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) // A[8]->$t0 add $t0, $s2, $t0 sw $t0, 48($s3) // $t0->A[12]

20

2004 Morgan Kaufmann Publishers

• Can refer to registers by name (e.g., $s2, $t2) instead of number
• Store word has destination last
• Remember arithmetic operands are registers, not memory!

Can’t write: add 48($s3), $s2, 32($s3)

Our First Example

• Can we figure out the code?

swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; swap:

21

2004 Morgan Kaufmann Publishers

v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

So far we’ve learned:

• MIPS

— loading words but addressing bytes — arithmetic on registers only

• Instruction

Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3

22

2004 Morgan Kaufmann Publishers

sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

• Instructions, like registers and words of data, are also 32 bits long

– Example: add $t1, $s1, $s2 – registers have numbers, $t1=9, $s1=17, $s2=18

• R-type Arithmetic Instruction Format:

6bits 5bits 5bits 5bits 5bits 6bits

Machine Language

23

2004 Morgan Kaufmann Publishers

6bits 5bits 5bits 5bits 5bits 6bits 000000 10001 10010 01001 00000 100000

• p

rs rt rd shamt funct

• Can you guess what the field names stand for?

• Consider the load-word and store-word instructions,

– Operands: two registers and a constant

• what problem using R-type format?

– What would the regularity principle have us do? – Design Principle 3: Good design demands a compromise

• Introduce a new type of instruction format

– I-type for data transfer instructions

Machine Language

24

2004 Morgan Kaufmann Publishers

– I-type for data transfer instructions

• Example: lw $t1, 32($s2)

35 18 9 32

• p

rs rt constant or address 6bits 5bits 5bits 16bits

• Where's the compromise?

Machine Language

Instr. Format

• p

rs rt rd shamt funct address add R Reg Reg Reg 3210 n.a. sub R Reg Reg Reg 3410 n.a. addi I 810 Reg Reg n.a. n.a. n.a. Constant lw I 3510 Reg Reg n.a. n.a. n.a. Address sw I 4310 Reg Reg n.a. n.a. n.a. Address

MIPS machine language encoding format

P.23

25

2004 Morgan Kaufmann Publishers

Example:

C code : A[300] = h + A[300]; Assembly code: lw $t0, 1200($t1) # reg $t0 gets A[300] add $t0, $s2, $t0 # reg $t0 gets h+A[300] sw $t0, 1200($t1) # store h+A[300] back to A[300]

8 9 45 32 8 8 18 8 9 35 funct Addr/ shamt rd rt rs

• p

Machine code:

1200 1200

• Assembly provides convenient symbolic representation

– much easier than writing down numbers – e.g., destination first

• Machine language is the underlying reality

– e.g., destination is no longer first

• Assembly can provide 'pseudoinstructions'

– e.g., “move $t0, $t1” exists only in Assembly

Assembly Language vs. Machine Language

26

2004 Morgan Kaufmann Publishers

– e.g., “move $t0, $t1” exists only in Assembly – would be implemented using “add $t0,$t1,$zero”

• When considering performance you should count real instructions

MIPS Logical Operation Instruction

• Logical Operations: Instructions that operate on fields of bits within

a word or on individual bits, pack and unpack of bits into words.

Logical op. C op Java op MIPS instr. shift left << << sll shift right >> >>> srl bit-by-bit AND & & and, andi

P21-1

27

2004 Morgan Kaufmann Publishers

• E.g.: sll $t2, $s0, 4 # $t2 = $s0 << 4bits

– rd = $t2, rt = $s0, and shamt (shift amount) = 4

bit-by-bit OR | |

• r, ori

bit-by-bit NOR ~ ( | ) ~ ( | ) nor

• p

rs rt rd shamt funct

16 10 4

Category Instr Example Meaning Comments Logical and and $s1, $s2, $s3 $s1 = $s2 & $s3 bit-by-bit AND

• r
• r $s1, $s2, $s3

$s1 = $s2 | $s3 bit-by-bit OR nor nor $s1, $s2, $s3 $s1 = ~($s2|$s3) bit-by-bit NOR andi andi $s1, $s2, 100 $s1 = $s2 & 100 AND with const

• ri
• ri $s1, $s2, 100

$s1 = $s2 | 100 OR with const. sll sll $s1, $s2, 10 $s1 = $s2 << 10 shift left by const srl srl $s1, $s2, 10 $s1 = $s2 >> 10 shift right by const P21-2

28

2004 Morgan Kaufmann Publishers

Name Format

• p

rs rt rd shamt func and R 18 19 17 36

• r

R 18 19 17 37 nor R 18 19 17 39 andi I 12 18 17

• ri

I 13 18 17 sll R 18 17 10 srl R 18 17 10 2

Assembly code MIPS Logical Instruction Machine code

100 100

• Stored Program Concept

– Instructions are bits – Programs are stored in memory

• to be read just like data

memory for data, programs, compilers, editors, etc.

MIPS Flow Control Instructions

29

2004 Morgan Kaufmann Publishers

• – Fetch & Execute Cycle
• Instructions are fetched and put into a special register
• Bits in the register "control" the subsequent actions
• Fetch the “next” instruction and continue

Processor Memory compilers, editors, etc.

• Decision making instructions

– alter the control flow, – i.e., change the "next" instruction to be executed

• MIPS conditional branch instructions:

bne $t0, $t1, Label

MIPS Flow Control Instructions

30

2004 Morgan Kaufmann Publishers

bne $t0, $t1, Label beq $t0, $t1, Label

• Example:

if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....

• MIPS unconditional branch instructions:

j label

• Example:

if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5 Lab2: ...

MIPS Flow Control Instructions

31

2004 Morgan Kaufmann Publishers

Lab2: ...

• Can you build a simple for loop?
• Can you build a simple while loop?

e.g., while (save[i] == k) i += 1;

?

MIPS Flow Control Instructions

• Example 2: while loop

– assume i, k correspond to $s3, $s5, and the base of the array save is in $s6

C code MIPS code while (save[i] == k) i += 1; Loop: sll $t1, $s3, 2 # $t1=i*4 add $t1, $t1, $s6 # $t1=addr of save[i]

24-1

Basic block

32

2004 Morgan Kaufmann Publishers

– Basic block: a sequence of instr. without branches (except possibly at the end) and without branch labels (except possibly at the beginning).

lw $t0, 0($t1) # $t0 = save[i] bne $t0, $s5, Exit # goto Exit if save[i]!=k add $s3, $s3, 1 # i=i+1 j Loop # goto loop Exit:

So far:

• Instruction

Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4 $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5

33

2004 Morgan Kaufmann Publishers

beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label

• Formats:
• p

rs rt rd shamt funct

• p

rs rt 16 bit address

• p

26 bit address R I J

• We have: beq, bne, what about Branch-if-less-than?
• New instruction:

if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0

• Can use this instruction to build "

"

Control Flow

34

2004 Morgan Kaufmann Publishers

• Can use this instruction to build "blt $s1, $s2, Label"

— can now build general control structures

• Note that the assembler needs a register to do this,

— there are policy of use conventions for registers

Policy of Use Conventions

Name Register number Usage $zero the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t7 8-15 temporaries

35

2004 Morgan Kaufmann Publishers

$t0-$t7 8-15 temporaries $s0-$s7 16-23 saved $t8-$t9 24-25 more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address

Register 1 ($at) reserved for assembler, 26-27 for operating system

• Small constants are used quite frequently (50% of operands)

e.g., A = A + 5; B = B + 1; C = C - 18;

• Solutions? Why not?

– put 'typical constants' in memory and load them. – create hard-wired registers (like $zero) for constants like zero.

Constants

36

2004 Morgan Kaufmann Publishers

– create hard-wired registers (like $zero) for constants like zero.

• MIPS Instructions:

addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6

• ri $29, $29, 4
• Design Principle 4: Make the common case fast.

Which format?

• We'd like to be able to load a 32 bit constant into a register
• Must use two instructions, new "load upper immediate" instruction

lui $t0, 1010101010101010

1010101010101010 0000000000000000

filled with zeros

How about larger constants?

37

2004 Morgan Kaufmann Publishers

• Then must get the lower order bits right, i.e.,
• ri $t0, $t0, 1010101010101010

1010101010101010 0000000000000000 0000000000000000 1010101010101010 1010101010101010 1010101010101010

• ri

• Instructions:

bne $t4,$t5,Label Next instruction is at Label if $t4$t5 beq $t4,$t5,Label Next instruction is at Label if $t4=$t5 j Label Next instruction is at Label

• Formats:
• p

rs rt 16 bit address I

Addresses in Branches and Jumps

38

2004 Morgan Kaufmann Publishers

• Addresses are not 32 bits

— How do we handle this with load and store instructions?

• Could specify a register (like lw and sw) and add it to address

– use Instruction Address Register (PC = program counter) – most branches are local (principle of locality)

• Jump instructions just use high order bits of PC

– address boundaries of 256 MB

• p

26 bit address J

Assembly to Machine Example

while (save[i] == k) i += 1; (Assume i in $s3, k in $s5, the base of the array save in $s6) Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1)

19 9 2 9 22 9 32 35 9 8

80000 80004 80008

39

2004 Morgan Kaufmann Publishers

bne $t0, $s5, Exit add $s3, $s3, 1 j Loop Exit:

5 8 21 2 8 19 19 1 2 20000

80008 80012 80016 80020 how to deal with the condition if conditional branch branches far away → assembler convert the statement into an unconditional branch and a inverse-conditional branch

• Ex. beq $s0, $s1, L1 →

bne $s0, $s1, L2 j L1 L2:

MIPS addressing mode

• 1. Immediate addressing:

– the operand is a constant inside the instr.

• 2. Register addressing:

– the operand is a register

• 3. Base or displacement addressing:

– the operand is at the memory location whose addr. is the

P.36-1

40

2004 Morgan Kaufmann Publishers

sum of a reg and a constant inside instr. (lw/sw/lh/sh/lb/sb)

• 4. PC-relative addressing:

– the address is a 16-bit constant in instr., shifted left 2 bits (word to byte), and then added to (PC+4). (i.e., next instr.)

• 5. Pseudodirect addressing:

– the address is a 26-bit constant in instruction, shifted left 2 bits (word to byte), and then concatenated with the 4 upper bits of PC. Address boundary: 228 = 256MB.

B yte H a lfw ord W o rd R eg is te rs M e m o r y R eg ister R e gister

• 1. Im m e diate a dd re s sing
• 2. R eg is ter ad dre ssin g
• 3. B as e ad dres sin g
• p

rs r t

• p

rs r t

• p

rs r t A d dres s rd . . . fu nc t Im m ed ia te

+

andi $s1, $s2, 100 and $s1, $s2, $s3 lw/lb/lh $s1, 100($s2)

41

2004 Morgan Kaufmann Publishers M e m o r y W o rd M e m o r y W o rd

• 4. P C -re la tive a dd re ssin g
• 5. P se ud o dire ct ad dres sin g
• p
• p

rs r t A d dres s A d d re ss P C P C

+

beq $s1, $s2, 100 j 10000

• Discussed in your assembly language programming lab:

support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions

Other Issues

42

2004 Morgan Kaufmann Publishers

system calls and conventions

• Some of these we'll talk more about later
• We’ll talk about compiler optimizations when we hit chapter 4.

Procedure Call

• Six steps for the execution of a procedure

– Place parameters in an accessible place to the procedure – Transfer the control to the procedure – Acquire the storage resources needed for the procedure – Perform the desired task – Place the result value in an accessible place to the calling program – Return control to the point of origin

• Definitions related to procedure

43

2004 Morgan Kaufmann Publishers

• Definitions related to procedure

– Return address – Program counter (PC) / instruction address register – Caller – Callee – Stack – Stack pointer – Spilling register

Procedure Call in MIPS

• Jump-and-link instruction: jal ProcedureAddress

– Put the parameter values in $a0-$a3 – Save the address of the instruction next to current instruction (PC + 4) to $ra – Jump to the ProcedureAddress

• Return scheme

– Put the return values in $v0-$v1

44

2004 Morgan Kaufmann Publishers

– Put the return values in $v0-$v1 – Return control to the caller using “jr $ra”

• Using more registers

Example for Procedure Call

int leaf_example (int g, int h, int i, int j) { int f; f = (g + h) – (i + j); return f; } leaf_example:

$a0 $a1 $a2 $a3 $s0 $t1 $t0

45

2004 Morgan Kaufmann Publishers

leaf_example: addi $sp, $sp, -12 sw $t1, 8($sp) sw $t0, 4($sp) sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) lw $t0, 4($sp) lw $t1, 8($sp) addi $sp, $sp, 12 jr $ra

Procedure – cont.

• The example in the previous slide we used registers $s0, $t0, $t1 in

the procedure so saved and restored them.

• To avoid saving and restoring a register whose value is never used,

MIPS software separate registers into two groups. – Data preservation in MIPS

Preserved Not preserved Saved registers: $s0 - $s7 Temporary registers: $t0 - $t9

46

2004 Morgan Kaufmann Publishers

– Preserved: The caller assumes them will be preserved on a procedure

• call. If they are used, the callee must save and restore them.
• In the example of previous slide, since the caller does not expect registers

$t0 and $t1 to be preserved across a procedure call, we can drop two stores and two loads from the code.

• But need to save and restore $s0 because caller expects it to be preserved.

Saved registers: $s0 - $s7 Temporary registers: $t0 - $t9 Stack pointer register: $sp Argument registers: $a0 - $a3 Return address register: $ra Return value registers: $v0 - $v1 Stack above the stack pointer Stack below the stack pointer

Memory Allocation on the Stack

• Procedure frame (activation record) – the segment of the stack

containing a procedure’s saved registers and local variables

• Frame pointer ($fp) – a value denoting the location of the saved

registers and local variables for a given procedure (point to the first word of the frame of a procedure.

• Why need $fp? Can’t $sp provide enough information for accessing

the data in the stack?

47

2004 Morgan Kaufmann Publishers

Memory Allocation on the Heap

• What’s the difference among automatic, static, and dynamic variables?

– Automatic – local to a procedure and discarded when procedure exits. – Static – exist across procedures. MIPS uses global pointer ($gp) points to

static data to simplify the access.

• Memory allocation

– Automatic: stack ($sp) – Static: static data segment ($gp + 16-bit 2’s complement offset)

local global Variable length

48

2004 Morgan Kaufmann Publishers

– Static: static data segment ($gp + 16-bit 2’s complement offset) – Dynamic: heap (1001 0000 ↑ ↑ ↑ ↑)

Constants, Static variables Text segment: the segment of a Unix object file that contains the machine language code for routines in the source file

1001 0000

Procedure Call Instruction Tables

MIPS assembly language Category Instruction Example Meaning Unconditional jump jump J L go to L Jump register Jr $ra Go to $ra Jump and link Jal L $ra = PC + 4; go to L

MIPS machine language Name Format Example comments

49

2004 Morgan Kaufmann Publishers

Name Format Example comments

j J 2 2500 J 10000 jr R 31 8 Jr $ra jal J 3 2500 jal 10000 Filed size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits R-format R

• p

rs rt rd shamt funct Arithmetic instruction format J-format J

• p

Target address Jump instruction format

• MIPS instr formats:

– Simple instructions all 32 bits wide – Very structured, no unnecessary baggage – Three instruction formats:

–

Overview of MIPS

Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits Fields Name Comments

50

2004 Morgan Kaufmann Publishers

– Rely on compiler to achieve performance – Help compiler where we can

Field size R-format I-format J-format 6 bits

• p
• p
• p

5 bits rs rs target address 5 bits rt rt 5 bits rd address/immediate 5 bits shamt 6 bits funct All MIPS instructions 32 bits Arithmetic instructions format Transfer, branch, imm. format Jump instruction format

FIGURE 3.19 MIPS instruction formats in Chapter 3.

• MIPS operands:

M IP S

• p

era n d s N am e E x am p le C

• m

m en ts $ s

• $

s 7 , $ t

• $

t 9 , $ z e r

• , F

a st lo ca tio n s fo r d a ta . In M IP S , d a ta m u st b e in re g iste rs to p e rfo rm

3 2 registers $ a

• $

a 3 , $ v

• $

v 1 , $ g p ,

a rith m e

• tic. M

IP S re g iste r $ ze ro a lw a ys e q u a ls 0 . R e g iste r $ a t is

$ f p , $ s p , $ r a , $ a t

re se rve d fo r th e a sse m b le r to h a n d le la rg e co n sta n ts.

Overview of MIPS

51

2004 Morgan Kaufmann Publishers

M em

• ry[0],

A cce sse d

• n

ly b y d a ta tra n sfe r in stru ctio n

• s. M

IP S u se s b yte a d d re sse s, so

2

3 0 m

em

• ry M

em

• ry[4], ...,

se q u e n tia l w

• rd

s d iffe r b y 4 . M e m

• ry h
• ld

s d a ta stru ctu re s, su ch a s a rra ys,

w

• rds

M em

• ry[4294

9672 92]

a n d sp ille d re g iste rs, su ch a s th

• se

sa ve d

• n

p ro ce d u re ca lls.

• MIPS assembly language:

MIPS assembly language Category Instruction Example Meaning Comments

add

add $s1, $s2, $s3 $s1 = $s2 + $s3

Three operands; data in registers

Arithmetic

subtract

sub $s1, $s2, $s3 $s1 = $s2 - $s3

Three operands; data in registers add immediate

addi $s1, $s2, 100 $s1 = $s2 + 100

Used to add constants load word

lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register

store word

sw $s1, 100($s2) Memory[$s2 + 100] = $s1

Word from register to memory

Data transfer

load byte

lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register

Overview of MIPS

52

2004 Morgan Kaufmann Publishers

store byte

sb $s1, 100($s2) Memory[$s2 + 100] = $s1

Byte from register to memory load upper immediate lui $s1, 100

$s1 = 100 * 2

16

Loads constant in upper 16 bits branch on equal

beq $s1, $s2, 25

if ($s1 == $s2) go to PC + 4 + 100 Equal test; PC-relative branch

Conditional

branch on not equal

bne $s1, $s2, 25

if ($s1 != $s2) go to PC + 4 + 100 Not equal test; PC-relative

branch

set on less than

slt $s1, $s2, $s3

if ($s2 < $s3) $s1 = 1; else $s1 = 0 Compare less than; for beq, bne set less than immediate

slti $s1, $s2, 100

if ($s2 < 100) $s1 = 1; else $s1 = 0 Compare less than constant jump

j 2500 go to 10000

Jump to target address

Uncondi-

jump register

jr $ra go to $ra

For switch, procedure return

tional jump

jump and link

jal 2500 $ra = PC + 4; go to 10000

For procedure call

Overview of MIPS

• MIPS machine language

Name Format Example comments

and R 18 (S2) 19 (S3) 17 (S1) 36 and $s1, $s2, $s3

• r

R 18 19 17 37

• r $s1, $s2, $s3

nor R 18 19 17 39 nor $s1, $s2, $s3 andi I 12 18 (S2) 17 (S1) 100 andi $s1, $s2, 100

• ri

I 13 18 (S2) 17 (S1) 100

• ri $s1, $s2, 100

sll R 18 17 10 sll $s1, $s2, 10

53

2004 Morgan Kaufmann Publishers

sll R 18 17 10 sll $s1, $s2, 10 srl R 18 17 10 2 srl $s1, $s2, 10 beq I 4 17 (S1) 18 (S2) 25 beq $s1, $s2, 100 bne I 5 17 18 25 bne $s1, $s2, 100 slt R 18 19 17 42 slt $s1, $s2, $s3 j J 2 2500 j 10000 Filed size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits R-format R

• p

rs rt rd shamt funct Arithmetic instruction format I-format I

• p

rs rt address Data transfer format

• Design alternative:

– provide more powerful operations – goal is to reduce number of instructions executed – danger is a slower cycle time and/or a higher CPI

Alternative Architectures

–“ “ “ “The path toward operation complexity is thus fraught with

54

2004 Morgan Kaufmann Publishers

• Let’s look (briefly) at IA-32

peril. To avoid these problems, designers have moved toward simpler instructions”

IA - 32

• 1978: The Intel 8086 is announced (16 bit architecture)
• 1980: The 8087 floating point coprocessor is added
• 1982: The 80286 increases address space to 24 bits, +instructions
• 1985: The 80386 extends to 32 bits, new addressing modes
• 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions

(mostly designed for higher performance)

• 1997: 57 new “MMX” instructions are added, Pentium II
• 1999: The Pentium III added another 70 instructions (SSE)
• 2001: Another 144 instructions (SSE2)

55

2004 Morgan Kaufmann Publishers

• 2001: Another 144 instructions (SSE2)
• 2003: AMD extends the architecture to increase address space to 64 bits,

widens all registers to 64 bits and other changes (AMD64)

• 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds

more media extensions

• “This history illustrates the impact of the “golden handcuffs” of compatibility

“adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explain and impossible to love”

IA-32 Overview

• Complexity:

– Instructions from 1 to 17 bytes long – one operand must act as both a source and destination – one operand can come from memory – complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement”

• Saving grace:

56

2004 Morgan Kaufmann Publishers

• Saving grace:

– the most frequently used instructions are not too difficult to build – compilers avoid the portions of the architecture that are slow “what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”

IA-32 Registers and Data Addressing

• Registers in the 32-bit subset that originated with 80386

GPR 0 GPR 1 GPR 2 GPR 3 GPR 4 GPR 5 Use 31 Name EAX ECX EDX EBX ESP EBP

57

2004 Morgan Kaufmann Publishers

GPR 5 GPR 6 GPR 7 Code segment pointer Stack segment pointer (top of stack) Data segment pointer 0 Data segment pointer 1 Data segment pointer 2 Data segment pointer 3 Instruction pointer (PC) Condition codes EBP ESI EDI CS SS DS ES FS GS EIP EFLAGS

IA-32 Register Restrictions

• Registers are not “general purpose” – note the restrictions below

58

2004 Morgan Kaufmann Publishers

IA-32 Typical Instructions

• Four major types of integer instructions:

– Data movement including move, push, pop – Arithmetic and logical (destination register or memory) – Control flow (use of condition codes / flags ) – String instructions, including string move and string compare

59

2004 Morgan Kaufmann Publishers

IA-32 instruction Formats

• Typical formats: (notice the different lengths)
• a. JE EIP + displacement
• b. CALL
• c. MOV EBX, [EDI + 45]

CALL JE Offset Displacement Condi- tion 4 4 8 8 32

60

2004 Morgan Kaufmann Publishers

• c. MOV EBX, [EDI + 45]
• d. PUSH ESI
• e. ADD EAX, #6765
• f. TEST EDX, #42

Immediate Postbyte TEST ADD PUSH MOV w w Immediate Reg Reg w d Displacement r/m Postbyte 6 8 1 1 8 5 3 4 32 3 1 7 32 1 8

• Instruction complexity is only one variable

– lower instruction count vs. higher CPI / lower clock rate

• Design Principles:

– simplicity favors regularity – smaller is faster – good design demands compromise – make the common case fast

Summary

61

2004 Morgan Kaufmann Publishers

– make the common case fast

• Instruction set architecture

– a very important abstraction indeed!