Josef Ressel Center for Verification of Embedded Computing Systems - - PowerPoint PPT Presentation

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Josef Ressel Center for Verification of Embedded Computing Systems - - PowerPoint PPT Presentation

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Josef Ressel Center for Verification of Embedded Computing Systems A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs IEEE I2MTC 2015 May 11-14, 2015 | Pisa, Italy Dominik Widhalm 1 , Stefan Tauner 1 ,

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SLIDE 1

Josef Ressel Center for Verification of Embedded Computing Systems

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs IEEE I2MTC 2015 May 11-14, 2015 | Pisa, Italy

Dominik Widhalm1, Stefan Tauner1, Martin Horauer1 Achim Schumacher2, Alexander Haggenmiller2

1UAS Technikum Wien, 2Infineon Technologies Austria AG

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SLIDE 2

ECU MC

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 1/17

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SLIDE 3

ECU MC

Agenda

1 Verification Efforts for Modern Automotive Microcontrollers 2 Bridging the Verification Gap(s)

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 1/17

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SLIDE 4

AURIX TC29xx

IOM HSSL DMA Bridge PMI FPU DMI TriCore 1.6P PMI FPU DMI TriCore 1.6P Checker Core PMI FPU DMI TriCore 1.6P Checker Core Shared Ressource Interconnect (SRI) BCU SCU STM GPT12x CCU6x Generic Timer Module (GTM) Embedded Voltage Regulator (EVR) 5V or 3.3V Single Supply LMU RAM QSPIx ASCLINx MultiCAN+ FlexRay Ethernet FCE I²C PSI5 SENT MSCx System Peripheral Bus (SPB) EBU Data Flash BROM Key Flash Program Memory Unit (PMU) Progr. Flash Progr. Flash OCDS Ports HSM DS-ADCx VADCx PLL

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 2/17

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SLIDE 5

AURIX TC29xx — ADCs

IOM HSSL DMA Bridge PMI FPU DMI TriCore 1.6P PMI FPU DMI TriCore 1.6P Checker Core PMI FPU DMI TriCore 1.6P Checker Core Shared Ressource Interconnect (SRI) BCU SCU STM GPT12x CCU6x Generic Timer Module (GTM) Embedded Voltage Regulator (EVR) 5V or 3.3V Single Supply LMU RAM QSPIx ASCLINx MultiCAN+ FlexRay Ethernet FCE I²C PSI5 SENT MSCx System Peripheral Bus (SPB) EBU Data Flash BROM Key Flash Program Memory Unit (PMU) Progr. Flash Progr. Flash OCDS Ports HSM DS-ADCx VADCx PLL

Analog DS Modulator Main Filter Chain

Analog Input(s)

Input Select Adjust Auxiliary Filter and Comparator

Result Service Req. Result Service Req. Digital Input

. . .

10 DS ADCs

  • Glob. Result

Register Request Sources Triggers, Service Requests Clock Control

. . . Arbiter

Result Handling S&H Unit

. . .

Converter

. . .

. . .

. . .

11 SAR-ADCs (8 channels each)

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 3/17

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SLIDE 6

Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 4/17

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SLIDE 7

Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 4/17

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SLIDE 8

AURIX Pre-Silicon Verification Activities

  • Simulation

→ AGENtiX & Cadence Tools (Incisive, Specman etc.)

  • Emulation

→ AGENtiX

  • Static Analysis

→ Cadence & Infineon Tools (e.g., GateCheck)

  • Equivalence Checks

→ Cadence Encounter (Conformal EC) & Infineon Tools (e.g., GateComp)

  • Assertion-based Verification (ABV)

→ Cadence & Infineon Tools (e.g., GateProp)

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 5/17

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SLIDE 9

AGENtiX — A SystemC Simulation Environment

TOP Specman Bridge

SC_THREAD3run3Iv 3333dacMsetI/l3X///v; 3333spi/MsendDataI/xFNv; 3333p//_/3=3SC_LOGIC_F; 3333spi/MreceiveDataIbv; 3333p//_/3=3SC_LOGIC_/; SC_THREAD3run3Iv 3333dacMsetI/l3X///v; 3333spi/MsendDataI/xFNv; 3333p//_/3=3SC_LOGIC_F; 3333spi/MreceiveDataIbv; 3333p//_/3=3SC_LOGIC_/;

Peripheral3specific MonitorsoBFMs

SC_THREAD3Isv 3333eMgM3runIv 3333for3Inbox MON MON BFM BFM TestbenchXxx IClusterv Message Router Clock Generator JTAG Host TCN Proxy TCF Proxy TC/ Proxy Pulse Generator Clock Generator

Basic3SC Testbench DUT

XTALF PORST JTAG3If

CPUF CPUN CPU/ L M N O P/ PF

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 6/17

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SLIDE 10

Post-Silicon Verification Activities

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 7/17

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SLIDE 11

AURIX Post-Silicon Verification Activities

  • SoC Testing

→ Clock distribution, reset handling, code execution, module interaction etc.

  • Mixed-signal testing

→ Module interaction, crosstalk etc.

  • Power tests

→ Power modes, envelope etc.

  • EMC conformance & ESD Tests
  • Robustness/stress tests

Lots of different tools and departments involved, e.g.:

  • PCB support and robustness testing in Bangalore, India
  • Flash tests in Munich, Germany
  • CPU verification in Bristol, GB
  • Two departments in Villach, Austria, with over 100 employees for

ADC, power, PLL etc. (numbers include non-verification-specific positions)

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 8/17

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SLIDE 12

ADC Post-Silicon Verification

  • Laboratory instruments & DUT controlled via VBA scripts in Excel
  • Relies on various DLLs for actual communication

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 9/17

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SLIDE 13

Classic Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 10/17

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SLIDE 14

Actual Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation Tier 1 Suppliers Manufacturer Customer

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 10/17

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SLIDE 15

Verification Gaps in the Design Flow

Cadence Tools / AGENtiX Excel Sheets / Matlab etc. User-mode test cases Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation Tier 1 Suppliers Manufacturer Customer

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 11/17

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SLIDE 16

Verification Gaps in the Design Flow

Cadence Tools / AGENtiX Excel Sheets / Matlab etc. User-mode test cases Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation Tier 1 Suppliers Manufacturer Customer

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 11/17

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SLIDE 17

Overview of Novel Bridging Approach

Simulation Environment (AGENtiX) Physical Environment Pre-Silicon Verification Post-Silicon Verification AGENtiX Converter Module Execution Module Legacy Environment Legacy Exchange Format Machine-readable T est Case Format Executable Image Legacy Converter Module Platform-Independent Environment User Input Human-readable T est Case Configuration Information T est Case Elements Environment- specific Information A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 12/17

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SLIDE 18

Overview of Novel Bridging Approach

Simulation Environment (AGENtiX) Physical Environment Pre-Silicon Verification Post-Silicon Verification AGENtiX Converter Module Execution Module Legacy Environment Legacy Exchange Format Machine-readable T est Case Format Executable Image Legacy Converter Module Platform-Independent Environment User Input Human-readable T est Case Configuration Information T est Case Elements Environment- specific Information A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 12/17

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SLIDE 19

Post-Silicon Approach

DUV T est Application OCDS

IOClient DAP (over USB) GPIB (over USB)

  • Lab. Equipment

Power supplies Multimeters Pattern Generators …

Host Physical Environment

Perl Interpreter Module T est Interpreter Human-readable T est Case Equipment/Pin Mapping Predefined Modules Human-readable T est Case Equipment/Pin Mapping Predefined Modules VISA GPIB Abstraction Device Access Server (DAS) Perlcore

Implementation

  • Interpreter loads and executes test

case

  • Communication with lab. equip. via

VISA/GPIB

  • Data transfer and synchronization

between DUT and host via DAS

Challenges

  • Synchronization between host and

DUT

  • Firmware generation directly out of

test cases

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 13/17

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SLIDE 20

Pre-Silicon Approach

Simulation Environment (AGENtiX) Physical Environment Pre-Silicon Verification Post-Silicon Verification AGENtiX Converter Module Execution Module Legacy Environment Legacy Exchange Format Machine-readable T est Case Format Executable Image Legacy Converter Module Platform-Independent Environment User Input Human-readable T est Case Configuration Information T est Case Elements Environment- specific Information A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 14/17

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SLIDE 21

Pre-Silicon Approach

Implementation

  • Global configuration value switches off control of real hardware
  • Enables output of SystemC code compatible with AGENtiX
  • SystemC code can then be simulated like ordinary testbenches

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 15/17

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SLIDE 22

Evaluation

  • Metric?
  • Full evaluation of speedup impossible: would require fabrication
  • f intentionally bad silicon and organizing a realistic bug hunt
  • Show feasibility only with creation of test cases

Example: Histogram Test

1 Apply constant voltage to ADC input 2 Trigger huge number of ADC

conversion

3 Calculate variance and deviation 4 Compare result with given limits

  • Requires synchronization and data

transfer between host and DUV

  • Needs to control laboratory

equipment

  • Successfully implemented with

proposed approach

HistogrambTest yes returnbPASS no returnbFAIL isbthebdeviation withinbtheblimits? calculatebthebvariance andbthebdeviation applybconstantbvoltage levelbtobthebADCbinput buildbhistogrambofbthe conversionbresults desiredbnumber

  • fbrepetitions

reached? yes no triggerbanbADCbconversion andbstorebthebresult A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 16/17

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SLIDE 23

Conclusion

Limitations

– Not all describable test cases can be used in all environments – Existing test cases have to be ported

Advantages

+ Describes test cases at a high level of abstraction + Considers both verification & validation issues in planning + Reduces overall test time by sharing test cases + Allows to back-annotate errors found + Enable links to other activities (e.g., characterization)

A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 17/17