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Josef Ressel Center for Verification of Embedded Computing Systems

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities IEEE Austrochip 2015 September 28, 2015 | Vienna, Austria

Stefan Tauner, Dominik Widhalm, Martin Horauer UAS Technikum Wien

ECU MC

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 1/19

ECU MC

Agenda

1 Verification efforts for modern automotive microcontrollers 2 Need for communication in post-silicon verification 3 Message-passing interface obeying real-time constraints

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 1/19

AURIX TC29xx

IOM HSSL DMA Bridge PMI FPU DMI TriCore 1.6P PMI FPU DMI TriCore 1.6P Checker Core PMI FPU DMI TriCore 1.6P Checker Core Shared Ressource Interconnect (SRI) BCU SCU STM GPT12x CCU6x Generic Timer Module (GTM) Embedded Voltage Regulator (EVR) 5V or 3.3V Single Supply LMU RAM QSPIx ASCLINx MultiCAN+ FlexRay Ethernet FCE I²C PSI5 SENT MSCx System Peripheral Bus (SPB) EBU Data Flash BROM Key Flash Program Memory Unit (PMU) Progr. Flash Progr. Flash OCDS Ports HSM DS-ADCx VADCx PLL

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 2/19

AURIX TC29xx — ADCs

IOM HSSL DMA Bridge PMI FPU DMI TriCore 1.6P PMI FPU DMI TriCore 1.6P Checker Core PMI FPU DMI TriCore 1.6P Checker Core Shared Ressource Interconnect (SRI) BCU SCU STM GPT12x CCU6x Generic Timer Module (GTM) Embedded Voltage Regulator (EVR) 5V or 3.3V Single Supply LMU RAM QSPIx ASCLINx MultiCAN+ FlexRay Ethernet FCE I²C PSI5 SENT MSCx System Peripheral Bus (SPB) EBU Data Flash BROM Key Flash Program Memory Unit (PMU) Progr. Flash Progr. Flash OCDS Ports HSM DS-ADCx VADCx PLL

Analog DS Modulator Main Filter Chain

Analog Input(s)

Input Select Adjust Auxiliary Filter and Comparator

Result Service Req. Result Service Req. Digital Input

. . .

10 DS ADCs

• Glob. Result

Register Request Sources Triggers, Service Requests Clock Control

. . . Arbiter

Result Handling S&H Unit

. . .

Converter

. . .

. . .

. . .

11 SAR-ADCs (8 channels each)

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 3/19

Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 4/19

Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 4/19

AURIX Pre-Silicon Verification Activities

• Simulation

→ AGENtiX & Cadence Tools (Incisive, Specman etc.)

• Emulation

→ AGENtiX

• Static Analysis

→ Cadence & Infineon Tools (e.g., GateCheck)

• Equivalence Checks

→ Cadence Encounter (Conformal EC) & Infineon Tools (e.g., GateComp)

• Assertion-based Verification (ABV)

→ Cadence & Infineon Tools (e.g., GateProp)

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 5/19

AGENtiX — A SystemC Simulation Environment

TOP Specman Bridge

SC_THREAD3run3Iv 3333dacMsetI/l3X///v; 3333spi/MsendDataI/xFNv; 3333p//_/3=3SC_LOGIC_F; 3333spi/MreceiveDataIbv; 3333p//_/3=3SC_LOGIC_/; SC_THREAD3run3Iv 3333dacMsetI/l3X///v; 3333spi/MsendDataI/xFNv; 3333p//_/3=3SC_LOGIC_F; 3333spi/MreceiveDataIbv; 3333p//_/3=3SC_LOGIC_/;

Peripheral3specific MonitorsoBFMs

SC_THREAD3Isv 3333eMgM3runIv 3333for3Inbox MON MON BFM BFM TestbenchXxx IClusterv Message Router Clock Generator JTAG Host TCN Proxy TCF Proxy TC/ Proxy Pulse Generator Clock Generator

Basic3SC Testbench DUT

XTALF PORST JTAG3If

CPUF CPUN CPU/ L M N O P/ PF

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 6/19

Post-Silicon Verification Activities

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 7/19

AURIX Post-Silicon Verification Activities

• SoC Testing

→ Clock distribution, reset handling, code execution, module interaction etc.

• Mixed-signal testing

→ Module interaction, crosstalk etc.

• Power tests

→ Power modes, envelope etc.

• EMC conformance & ESD Tests
• Robustness/stress tests

Lots of different tools and departments involved, e.g.:

• PCB support and robustness testing in Bangalore, India
• Flash tests in Munich, Germany
• CPU verification in Bristol, GB
• Two departments in Villach, Austria, with over 100 employees for

ADC, power, PLL etc. (numbers include non-verification-specific positions)

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 8/19

ADC Post-Silicon Verification

• Laboratory instruments & DUT controlled via VBA scripts in Excel
• Relies on various DLLs for actual communication

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 9/19

Classic Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 10/19

Actual Design Flow

Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation Tier 1 Suppliers Manufacturer Customer

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 10/19

Verification Gaps in the Design Flow

Cadence Tools / AGENtiX Excel Sheets / Matlab, ATEs etc. User-mode test cases Specification High-Level Design Low-Level Design RTL Coding (IP & System Level) Gate-Level Simulation Functional Verification Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Verification Firmware, Drivers, System Software Design and Validation Tier 1 Suppliers Manufacturer Customer

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 11/19

Overview of Bridging Approach

Simulation Environment (AGENtiX) Physical Environment Pre-Silicon Verification Post-Silicon Verification AGENtiX Converter Module Execution Module Legacy Environment Legacy Exchange Format Machine-readable T est Case Format Executable Image Legacy Converter Module Platform-Independent Environment User Input Human-readable T est Case Configuration Information T est Case Elements Environment- specific Information Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 12/19

Overview of Bridging Approach

Simulation Environment (AGENtiX) Physical Environment Pre-Silicon Verification Post-Silicon Verification AGENtiX Converter Module Execution Module Legacy Environment Legacy Exchange Format Machine-readable T est Case Format Executable Image Legacy Converter Module Platform-Independent Environment User Input Human-readable T est Case Configuration Information T est Case Elements Environment- specific Information Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 12/19

Automatic Test Equipment (ATE) Setup

• Primarily used for production tests & characterization
• Dozens or even hundreds of DUTs in parallel
• Communication with individual DUTs hard/costly

DUT Automatic T est Equipment

Parallel Data Transfer Host Software Sync. Stimuli Hardware

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 13/19

Lab Bench Setup

• Investigate interaction between modules
• Reenact actual use cases to debug problems
• Create reproducible failure scenarios

Power Supply Instrumentation Interface

(e.g., GPIB, PXI, LXI)

Communication & Debug Interface Digital Multimeter Pattern Generator

DUT Host

Parallel Data Transfer Sync.

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 14/19

Use Case — Simple ADC Histogram Test

1 Apply constant voltage to

ADC input

2 Trigger huge number of ADC

conversion

3 Calculate variance and

deviation

4 Compare result with given

limits

• Requires to synchronize
• utput of laboratory

equipment with firmware execution

• Additional data transfers

needed between host and DUT

HistogrambTest yes returnbPASS no returnbFAIL isbthebdeviation withinbtheblimits? calculatebthebvariance andbthebdeviation applybconstantbvoltage levelbtobthebADCbinput buildbhistogrambofbthe conversionbresults desiredbnumber

• fbrepetitions

reached? yes no triggerbanbADCbconversion andbstorebthebresult

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 15/19

Library Features

• Real-time-friendly message-passing interface
• API functions for synchronization/coordination and data transfer
• Layered approach for a modular design

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 16/19

Library Features

• Real-time-friendly message-passing interface
• API functions for synchronization/coordination and data transfer
• Layered approach for a modular design
• Comm. HW

Hardware Drivers

• Sync. & Comm.

Library Test Application

Hardware-dependent but interchangeable Stable API towards application Stable API towards drivers

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 16/19

Real-time Behavior

• No direct control by the host
• Shared buffer (e.g., communication interface FIFOs)
• Requests by host processed by DUT when appropriate
• Processing in bounded time ensures adherence to deadlines
• Sync. & Comm.

Library Test Application Buffer in

• Comm. HW

Controlling Host

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 17/19

Evaluation

• Library and test use case were implemented so far on 6 diverse

platforms with microcontrollers based on Atmel AVR and ARM Cortex-M4 cores, and on Infineon Aurix.

• Communication interfaces evaluated:
• UART
• USB
• OCD

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 18/19

Evaluation

• Library and test use case were implemented so far on 6 diverse

platforms with microcontrollers based on Atmel AVR and ARM Cortex-M4 cores, and on Infineon Aurix.

• Communication interfaces evaluated:
• UART
• USB
• OCD

Results

• Library code alone uses (depending on native word width) 1 kB

to 1.75 kB of flash space and 10 B to 16 B of static RAM

• Resource usage of hardware drivers ranges. . .
• from less than 100 B flash and 8 bytes of RAM
• to multiple kB of flash and many hundred bytes of RAM for caches

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 18/19

Conclusion

Recap

• Communication between DUT and test controller required
• Firmware on DUT may have real-time constraints

Generic Synchronization and Communication Library

• Modular design ↔ Hardware abstraction
• Full real-time compatibility
• Feasibility proven on various platforms

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 19/19

Sync — host first

⑥ ⑤

PC

sync step to 1 request #1 SYNC=0 process request #1 EAGAIN

API Services Sync IF User-mode Test

processs()

process request speed class 0

sync step to 1 request #2

① ② ③

sync_step() sync step SYNC OK

try to step to 1

HOST=0 DUT=0 Main Application process request #2

process request speed class 0

DUT=1 SYNC=1 HOST=1

⑦ ④

Synchronization Approaches for Testing Mixed-Signal SoCs under Real-Time Constraints using On-Chip Capabilities 20/19

Sync — DUT first

②

PC

sync step to 1 request #1 SYNC=0

API Services Sync IF User-mode Test

processs()

① ③ ④

sync_step() sync step SYNC OK

try to step to 1

HOST=0 DUT=0 Main Application process request #1

process request speed class 0*

DUT=1 HOST=1

⑤

SYNC=1 sync step

try to step to 1

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