Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, - - PowerPoint PPT Presentation

invyswell a hytm for haswell rtm
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Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, - - PowerPoint PPT Presentation

Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy Multicore Performance Scaling u Problem: Locking u Solution: HTM? u IBM BG/Q, zEC12, POWER u Intel Haswell TSX


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Invyswell: A HyTM for Haswell RTM

Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy

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2

Source: embedded.com

Multicore Performance Scaling

u Problem: Locking u Solution: HTM?

u IBM BG/Q, zEC12,

POWER

u Intel Haswell TSX

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Restricted Transactional Memory (RTM)

xbegin() xend() Atomic region called transaction Execute optimistically, without any locks Read and Write Sets Abort on memory conflict: programmer defined behavior

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RTM Fallback: Global Lock

if (xbegin() == XBEGIN_STARTED) xend() Execute Transaction else Execute Fallback Path

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Source: Anand Tech

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Lock Elision

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Why Lock Elision Is Not Enough

0 ¡ 0.5 ¡ 1 ¡ 1.5 ¡ 2 ¡ 2.5 ¡ 3 ¡ 3.5 ¡ 4 ¡ 4.5 ¡ 1 ¡ 2 ¡ 4 ¡ 8* ¡ Speedup ¡ Threads ¡ NorecSTM ¡ NorecHy ¡ HLE ¡

Labyrinth

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u [Gottschlich et al., CGO 2010] u Scalable u Good for large transactions u Conflict detection using bloom filters

7

InvalSTM (prior work)

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SW Txn

Time Commit Invalidation

8

InvalSTM Software Transaction (prior work)

update memory Main body of SW txn On read: Add to read Bfilter On write: Add to write Bfilter Add writes to hash table If can_commit() Invalidation Else restart

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InvalSTM Invalidation (prior work)

Committing Transaction Inflight Transactions Contention Manager

Can I commit? C

  • n

f l i c t s ? ( u s i n g b l

  • m

f i l t e r s )

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InvalSTM Invalidation (prior work)

Committing Transaction Inflight Transactions

no yes no A B O R T

Contention Manager

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11

Aborted Inflight Transactions Contention Manager

InvalSTM Invalidation (prior work)

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Committing Transaction Inflight Transactions

no yes no C O M M I T

Contention Manager

InvalSTM Invalidation (prior work)

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13

InvalSTM Invalidation (prior work)

Committed Inflight Transactions

I N V A L I D A T E

Contention Manager

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SW Txn

Time Commit Invalidation

14

Software Transaction (InvalSTM)

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HW Txn

Commit Invalidation

ABORT

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Hardware Transaction + Invalidation

Time

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HW Txn

Commit (Check BF) Invalidation

COMMIT

Already committed, can’t abort

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Hardware Transaction + Invalidation

Time

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SW Txn

Commit Invalidation

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Software Transaction (Modified InvalSTM)

Time

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SW Transaction 1 (commit) x++; y++; (invalidation) x = 2; y = 1; SW Transaction 2 (execution) Read x; Read y; z = 1/(x - y);

Time

ABORT

z = 1/0!!!

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SW Transaction 2 (execution) Read x; Read y; z = 1/(x - y);

19

Read Validation

SW Transaction 1 (commit) x++; y++;

Time

Check BF Check BF

ABORT

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20

SPECSW (Speculative Software)

SW

Time

Commit

Acquire commit_lock Validate If can_commit() update memory Else release lock and restart Main body of SW txn On read: Validate and add to read Bfilter On write: Add to write Bfilter Add writes to hash table

Post- Commit

Invalidation Decrement sw_cnt, release lock Begin SW txn, increment sw_cnt

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BFHW (Bloom Filters Hardware)

HW Commit

if (commit_lock) if (BF conflict()) xabort() xend() Main body of HW txn. On Read: add to read Bfilter On Write: add to write Bfilter

Post- Commit

Invalidation Time xbegin()

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HW Transaction 1 (commit) x++; y++; (invalidation) x = 2; y = 1; SW Transaction 2 (execution) Read x; Read y; z = 1/(x - y);

Time

ABORT

z = 1/0!!!

ABORT

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23

Read Validation

HW Transaction 1 (commit) x++; y++; SW Transaction 2 (execution) Read x; Read y; z = 1/(x - y);

Time

Check BF Check BF

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BFHW

HW Commit

if (commit_lock) if (BF_conflict()) xabort() ++hw_post_commit; xend() Main body of HW txn. On Read: add to read Bfilter On Write: add to write Bfilter

Post- Commit

Invalidation

  • -hw_post_commit (fetch_and_sub)

Time xbegin()

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25

Read Validation

HW Transaction 1 (commit) x++; y++; SW Transaction 2 (execution) Read x; Read y; z = 1/(x - y);

Time

Wait for hw_post_commit == 0 Wait for hw_post_commit == 0

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26

BFHW

HW Commit Post- Commit

Time

SPECSW

SW Commit Post- Commit

On Read: add to read Bfilter On Write: add to write Bfilter Invalidation

Expensive! Expensive!

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LITEHW (Light Hardware)

HW Commit

if (sw_cnt) xabort(); else xend() Main body of HW txn. Time xbegin()

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Committing SW Transaction Contention Manager Inflight Transactions

Ensuring Progress

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Ensuring Progress

Committing SW Transaction Inflight Transactions Committing HW Transaction Contention Manager

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IRREVOCSW (Irrevocable Software)

SW

Acquire commit lock, increment sw_cnt

Commit

Do nothing (Changes are already committed) Main body of SW txn. On Read: add to read Bfilter On Write: add to write Bfilter Use direct updates

Post- Commit

Invalidation Decrement sw_cnt, release lock Time

Expensive! Expensive! Does not abort – Guarantees Progress

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SGLSW (Single-Global-Lock Software)

SW

Acquire commit lock, increment sw_cnt ++commit_sequence

Commit

Do nothing (Changes are already committed) Main body of SW txn. Use direct updates

Post- Commit

++commit_sequence Decrement sw_cnt, release lock Time

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LiteHW BFHW SpecSW IrrevocSW

retry retry retry conflict

SW txns running?

yes no retry threshold exceeded

SglSW

large txns with unsupported HTM instructions / overflow small txns with unsupported HTM instructions retry threshold exceeded retry threshold exceeded

Start

Invyswell State Diagram

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LiteHW BFHW SpecSW

retry retry retry

SW txns running? Fail-fast?

yes no

SglSW

large txns with unsupported HTM instructions / overflow small txns with unsupported HTM instructions / fail-fast retry threshold exceeded retry threshold exceeded no yes

Start

Invyswell State Diagram

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Concurrent Execution Matrix

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Speedup

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Speedup

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Speedup

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Transaction Types – 1 Thread

benchmarks % transactions

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Transaction Types – 8 Threads

benchmarks % transactions

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u HLE and RTM w/ SGL fallback are not enough u Invyswell is 35% faster than NOrec, 18% faster than

Hybrid NOrec and 25% faster than HLE across all STAMP benchmarks

Conclusions

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Thank you!

u http://cs.brown.edu/~irina u irina@cs.brown.edu