Investigation of the front end electronics for the proton radius - - PowerPoint PPT Presentation

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Investigation of the front end electronics for the proton radius - - PowerPoint PPT Presentation

Apr 08, 2023 270 likes •464 views

Investigation of the front end electronics for the proton radius experiments Alexander Inglessi PNPI Gatchina TPC Collaboration Meeting 10 March 2020 TU Mainz TPC prototype Active target: gas target + ionization chamber 4 64 8

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SLIDE 1

Investigation of the front end electronics for the proton radius experiments

Alexander Inglessi • PNPI Gatchina TPC Collaboration Meeting • 10 March 2020 • TU Mainz

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SLIDE 2

TPC prototype

Projectile Recoil Anode Grid Cathode Z

V 3mm 200mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 29 47 48 51 52 55 56 58 59 60 61 62 63 64 30 31 32 27 26 28 36 35 34 33 57 53 45 49 41 37 54 50 46 42 43 44 40 39 38 65 66

Active target: gas target + ionization chamber

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SLIDE 3

Front-end prototype

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SLIDE 4

SIS3316 VME digitizers

  • 16 channels per module
  • 25 MHz (40 ns bin),

up to 250 MHz

  • 14 bit, 5 V (2 V) range
  • Int./ext. trigger
  • MAW energy/threshold
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SLIDE 5

Individual signal analysis

  • Signal smoothing
  • Peak search
  • Obtaining time

parameters by slope differentiation

  • Pedestal correction
  • Peak raw signal

integration → energy

11800 12000 12200 12400 12600 12800 13000 13200 13400 13600 13800 14000 100 200 300 400 500 600 700 800 900 1000 "signal_b20a75.txt" u 1:2 "signal_b20a75.txt" u 1:6 "signal_b20a75.txt" u 1:7 "signal_b20.txt" u 1:5 11950 12000 12050 12100 12150 12200 12250 400 450 500 550 600 650 "signal_b20a75.txt" u 1:2 "signal_b20a75.txt" u 1:6 "signal_b20a75.txt" u 1:7 "signal_b20.txt" u 1:5

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SLIDE 6

Recoil track search

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 29 47 48 51 52 55 56 58 59 60 61 62 63 64 30 31 32 27 26 28 36 35 34 33 57 53 45 49 41 37 54 50 46 42 43 44 40 39 38 65 66

  • Initial algorithm

implementation

  • Tested in beam

experiments with different detector

  • rientation
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SLIDE 7

Test station at GSI

Amplifier Signal generator (CAEN DT5800D) MBS, Nyx

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SLIDE 8

Generated amplifier input signals

α-signals. τGA= 0.5 ms

1000 2000 3000 4000 5000 6000 1 2 3 4 5 6 t, ms I, channel

Θ = 4.3 deg

α-signals. τGA= 0.5 ms

200 400 600 800 1000 1200 1400 1 2 3 4 5 6 t, ms I, channel Θ = 73.2 deg

19 21 24 26 29 31

t, us

11800 12240 12680 13120 13560 14000

Voltage, ch.

19 21 24 26 29 31

t, us

11800 12240 12680 13120 13560 14000

Voltage, ch.

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SLIDE 9

Amplifier shaping time: 1.4 and 0.4 μs

1.4 us shaping 0.4 us shaping 19 21 24 26 29 31 t, us 1e+04 1e+04 1e+04 1e+04 1e+04 2e+04 Voltage, ch.

4.3° recoil

1.4 us shaping 0.4 us shaping 19 21 24 26 29 31 t, us 11800 12440 13080 13720 14360 15000 Voltage, ch.

73.2° recoil

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SLIDE 10

Results: energy vs. Vin (short signal)

E1, AU E2, AU Ehw, AU Fit to 'E1, AU' Fit to 'Ehw, AU' 4 8 13 17 21 Vin, mV 18 35 53 70 88 Energies, AU E1_sigma, AU E2_sigma, AU Ehw_sigma, AU 4 8 13 17 21 Vin, mV 0.0 0.4 0.8 1.2 1.6 2.0

  • Std. dev., AU

1 AU ≈ 27 keV

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SLIDE 11

Results: integral vs. signal width

E (IKAR) E (simple) E (IKAR, left ped. cor.) 15 29 44 59 73 Theta, ° 82.1 82.9 83.7 84.5 85.3 86.1 E1

  • Energy must be

corrected

  • Individual channel

calibration required

1 AU ≈ 27 keV

1.4 us shaping 0.4 us shaping 19 21 24 26 29 31 t, us 1e+04 1e+04 1e+04 1e+04 1e+04 2e+04 Voltage, ch.

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SLIDE 12

Results: FADC trigger thresholds

0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2

1.4 μs, 60PT, 60GT

0.1° recoil, "2mv" threshold

mV Count %

0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2

1.4 μs, 60PT, 60GT

12.5° recoil, "2mv" threshold

mV Count %

0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.2 0.4 0.6 0.8 1 1.2

0.4 μs, 60PT, 60GT

0.1° recoil, "2mv" threshold

mV Count %

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0.2 0.4 0.6 0.8 1 1.2

0.4 μs, 60PT, 60GT

12.5° recoil, "2mv" threshold

mV Count %

~60 keV 1.4 μs shaping 0.4 μs shaping 0.1° recoil 12.5° recoil tuning in progress

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SLIDE 13

Shaping time optimization

  • time vs. energy resolution
  • full integration vs. beam influence minimization
  • smaller shaping for beam anode?
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SLIDE 14

Fast FADC readout

  • 5 FADCs with 1 Gbit/s Ethernet
  • 10 Gbit/s PC link
  • ~480 MB/s throughput achieved
  • 20x faster than current setup

SIS3316 10G Switch Test by SIS GmbH

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SLIDE 15

Conclusions

  • High time and energy resolution requirements
  • Energy must be corrected
  • Thresholds may be lowered
  • Time resolution studies with generator are in progress
  • Algorithm optimization needed for smaller shaping time

(noise filters, possibly higher sampling rate?)

  • Goal: final front-end electronics recommendation this

year

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SLIDE 16

Thank you!

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SLIDE 17

CAEN DT5800D Digital Detector Emulator

  • 2 analog outputs
  • 16 bit D/A converter
  • 125 Msamples/s
  • Constant/Poisson rate
  • 4096 points to store waveforms
  • White noise, 1/f noise emulation
  • Random Walk (baseline drift)
  • Interference generation
  • USB, Windows control app
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SLIDE 18

Moving average window